linux-dev/drivers/devfreq/Kconfig, branch linus/master

PM / devfreq: sun8i: addd COMMON_CLK dependency

2021-12-16T02:19:34Z

Compile-testing the driver without CONFIG_COMMON_CLK causes a link failure: arm-linux-gnueabi-ld: drivers/devfreq/sun8i-a33-mbus.o: in function `sun8i_a33_mbus_remove': sun8i-a33-mbus.c:(.text+0x450): undefined reference to `clk_rate_exclusive_put' arm-linux-gnueabi-ld: sun8i-a33-mbus.c:(.text+0x460): undefined reference to `clk_rate_exclusive_put' arm-linux-gnueabi-ld: drivers/devfreq/sun8i-a33-mbus.o: in function `sun8i_a33_mbus_probe': sun8i-a33-mbus.c:(.text+0x85c): undefined reference to `clk_rate_exclusive_get' arm-linux-gnueabi-ld: sun8i-a33-mbus.c:(.text+0x878): undefined reference to `clk_rate_exclusive_get' Fixes: 8bfd4858b4bb ("PM / devfreq: Add a driver for the sun8i/sun50i MBUS") Signed-off-by: Arnd Bergmann Signed-off-by: Chanwoo Choi

PM / devfreq: Add a driver for the sun8i/sun50i MBUS

2021-12-10T06:56:07Z

This driver works by adjusting the divider on the DRAM controller's module clock. Thus there is no fixed set of OPPs, only "full speed" down to "quarter speed" (or whatever the maximum divider is on that variant). It makes use of the MDFS hardware in the MBUS, in "DFS" mode, which takes care of updating registers during the critical section while DRAM is inaccessible. This driver should support several sunxi SoCs, starting with the A33, which have a DesignWare DDR3 controller with merged PHY register space and the matching MBUS register layout (so not A63 or later). However, the driver has only been tested on the A64/H5, so those are the only compatibles enabled for now. Acked-by: Chanwoo Choi Signed-off-by: Samuel Holland Signed-off-by: Chanwoo Choi

PM / devfreq: imx8m-ddrc: Remove DEVFREQ_GOV_SIMPLE_ONDEMAND dependency

2021-05-21T04:16:21Z

The driver can't support simple ondemand governor due to missing .get_dev_status() capability. Signed-off-by: Dong Aisheng Signed-off-by: Chanwoo Choi

PM / devfreq: Fix the wrong set_freq path for userspace governor in Kconfig

2021-04-08T04:14:50Z

Fix the wrong set_freq path for userspace governor in Kconfig. Signed-off-by: Dong Aisheng Signed-off-by: Chanwoo Choi

PM / devfreq: tegra20: Deprecate in a favor of emc-stat based driver

2020-11-23T07:01:13Z

Remove tegra20-devfreq in order to replace it with a EMC_STAT based devfreq driver. Previously we were going to use MC_STAT based tegra20-devfreq driver because EMC_STAT wasn't working properly, but now that problem is resolved. This resolves complications imposed by the removed driver since it was depending on both EMC and MC drivers simultaneously. Acked-by: Chanwoo Choi Signed-off-by: Dmitry Osipenko Signed-off-by: Chanwoo Choi

PM / devfreq: tegra20: Relax Kconfig dependency

2020-10-26T03:15:43Z

The Tegra EMC driver now could be compiled as a loadable kernel module. Currently devfreq driver depends on the EMC/MC drivers in Kconfig, and thus, devfreq is forced to be a kernel module if EMC is compiled as a module. This build dependency could be relaxed since devfreq driver checks MC/EMC presence on probe, allowing kernel configuration where devfreq is a built-in driver and EMC driver is a loadable module. This change puts Tegra20 devfreq Kconfig entry on a par with the Tegra30 devfreq entry. Acked-by: Chanwoo Choi Signed-off-by: Dmitry Osipenko Signed-off-by: Chanwoo Choi

PM / devfreq: Add generic imx bus scaling driver

2020-05-28T09:02:39Z

Add initial support for dynamic frequency switching on pieces of the imx interconnect fabric. All this driver does is set a clk rate based on an opp table, it does not map register areas. Signed-off-by: Leonard Crestez Tested-by: Martin Kepplinger Acked-by: Chanwoo Choi Signed-off-by: Chanwoo Choi

PM / devfreq: exynos: Rename Exynos to lowercase

2020-01-06T01:50:09Z

Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Chanwoo Choi

PM / devfreq: rk3399_dmc: Add COMPILE_TEST and HAVE_ARM_SMCCC dependency

2019-12-30T00:59:06Z

To build test, add COMPILE_TEST depedency to both ARM_RK3399_DMC_DEVFREQ and DEVFREQ_EVENT_ROCKCHIP_DFI configuration. And ARM_RK3399_DMC_DEVFREQ used the SMCCC interface so that add HAVE_ARM_SMCCC dependency to prevent the build break. Reported-by: kbuild test robot Signed-off-by: Chanwoo Choi

PM / devfreq: Add dynamic scaling for imx8m ddr controller

2019-12-30T00:59:05Z

Add driver for dynamic scaling the DDR Controller on imx8m chips. Actual frequency switching is implemented inside TF-A, this driver wraps the SMC calls and synchronizes the clk tree. The DRAM clocks on imx8m have the following structure (abridged): +----------+ |\ +------+ | dram_pll |-------|M| dram_core | | +----------+ |U|---------->| D | /--|X| | D | dram_alt_root | |/ | R | | | C | +---------+ | | |FIX DIV/4| | | +---------+ | | composite: | | | +----------+ | | | | dram_alt |----/ | | +----------+ | | | dram_apb |-------------------->| | +----------+ +------+ The dram_pll is used for higher rates and dram_alt is used for lower rates. The dram_alt and dram_apb clocks are "imx composite" and their parent can also be modified. This driver will prepare/enable the new parents ahead of switching (so that the expected roots are enabled) and afterwards it will call clk_set_parent to ensure the parents in clock framework are up-to-date. The driver relies on dram_pll dram_alt and dram_apb being marked with CLK_GET_RATE_NOCACHE for rate updates. Signed-off-by: Leonard Crestez Acked-by: Chanwoo Choi [cw00.choi: Edit the COMPILE_TEST module dependency in Kconfig] Signed-off-by: Chanwoo Choi