<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/dma/ioat/registers.h, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/dma/ioat/registers.h?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/dma/ioat/registers.h?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2019-05-21T09:28:40Z</updated>
<entry>
<title>treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 7</title>
<updated>2019-05-21T09:28:40Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-19T13:51:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9ab65aff02e842b09fbdcd7a7df02b63ed63442a'/>
<id>urn:sha1:9ab65aff02e842b09fbdcd7a7df02b63ed63442a</id>
<content type='text'>
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license as published by
  the free software foundation either version 2 of the license or at
  your option any later version this program is distributed in the
  hope that it will be useful but without any warranty without even
  the implied warranty of merchantability or fitness for a particular
  purpose see the gnu general public license for more details the full
  gnu general public license is included in this distribution in the
  file called copying

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-or-later

has been chosen to replace the boilerplate/reference in 9 file(s).

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Reviewed-by: Steve Winslow &lt;swinslow@gmail.com&gt;
Reviewed-by: Kate Stewart &lt;kstewart@linuxfoundation.org&gt;
Reviewed-by: Jilayne Lovejoy &lt;opensource@jilayne.com&gt;
Reviewed-by: Allison Randal &lt;allison@lohutok.net&gt;
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190519154041.244154651@linutronix.de
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: ioatdma: support latency tolerance report (LTR) for v3.4</title>
<updated>2019-02-25T06:48:38Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2019-02-22T17:00:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=528314b503f855b268ae7861ea4e206fbbfb8356'/>
<id>urn:sha1:528314b503f855b268ae7861ea4e206fbbfb8356</id>
<content type='text'>
IOATDMA 3.4 supports PCIe LTR mechanism. The registers are non-standard
PCIe LTR support. This needs to be setup in order to not suffer performance
impact and provide proper power management. The channel is set to active
when it is allocated, and to passive when it's freed.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>dmaengine: ioatdma: add descriptor pre-fetch support for v3.4</title>
<updated>2019-02-25T06:48:38Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2019-02-22T17:00:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e0100d40906d5dbe6d09d31083c1a5aaccc947fa'/>
<id>urn:sha1:e0100d40906d5dbe6d09d31083c1a5aaccc947fa</id>
<content type='text'>
Adding support for new feature on ioatdma 3.4 hardware that provides
descriptor pre-fetching in order to reduce small DMA latencies.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
</content>
</entry>
<entry>
<title>i7300_idle: Remove this driver</title>
<updated>2016-11-18T11:07:56Z</updated>
<author>
<name>Len Brown</name>
<email>len.brown@intel.com</email>
</author>
<published>2016-11-18T06:23:17Z</published>
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<id>urn:sha1:b65ce83f2a607ad478c5492812f5f218e8d57a6b</id>
<content type='text'>
In preparation for removing the idle_notifier, remove its only user, the
i7300_idle driver.

i7300_idle was deployed in 2008 to reduce idle memory power on systems
using the i7300 chipset.  The driver worked by throttling the
fully-buffered DIMMs during idle periods using the IOAT DMA engine.

The driver ran only on the i7300 chip-set, and no other hardware has used
this mechanism.  The driver no longer has a maintainer.

Removing this driver will increase idle power on i7300 systems when they
run the new kernel without the driver.

Signed-off-by: Len Brown &lt;len.brown@intel.com&gt;
Acked-by: Ingo Molnar &lt;mingo@kernel.org&gt;
Acked-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: http://lkml.kernel.org/r/ad6a044e57cc75f44cc8621abe846e58f7882243.1479449716.git.len.brown@intel.com
Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;

</content>
</entry>
<entry>
<title>dmaengine: ioatdma: Add error handling to ioat driver</title>
<updated>2016-08-08T02:41:42Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2016-07-20T20:13:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9546d4cdc8445acdea415f70a330bbfbd016a0f0'/>
<id>urn:sha1:9546d4cdc8445acdea415f70a330bbfbd016a0f0</id>
<content type='text'>
Adding error handling to the ioatdma driver so that when a
read/write error occurs the error results are reported back and
all the remaining descriptors are aborted. This utilizes the new
dmaengine callback function that allows reporting of results.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Reviewed-by: Lars-Peter Clausen &lt;lars@metafoo.de&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: ioatdma: disable relaxed ordering for ioatdma</title>
<updated>2016-05-14T08:06:52Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2016-05-11T21:32:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=511deae0261c839461948f2d4d1c13b8c8a59cd8'/>
<id>urn:sha1:511deae0261c839461948f2d4d1c13b8c8a59cd8</id>
<content type='text'>
ioatdma by default is in snoop mode. Relaxed ordering according to spec
does not do anything in snoop mode. However, it causes hang or significant
performance degrade when tested with NTB. Disabling in the driver due to
some BIOS do not configure it correctly.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: IOATDMA: Cleanup pre v3.0 chansts register reads</title>
<updated>2015-11-16T03:40:46Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2015-11-06T20:24:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d3cd63f91b84c60e0b30ee8a45b8f291dac7bbff'/>
<id>urn:sha1:d3cd63f91b84c60e0b30ee8a45b8f291dac7bbff</id>
<content type='text'>
Remove pre-3.0 channel status reads. 3.0 and later chansts register
is 64bit and can be read 64bit. This was clarified with the hardware
architects and since the driver now only support 3.0+ we don't need the
legacy support

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>dmaengine: Remove FSF mailing addresses</title>
<updated>2015-03-16T16:58:15Z</updated>
<author>
<name>Jarkko Nikula</name>
<email>jarkko.nikula@linux.intel.com</email>
</author>
<published>2015-03-16T07:37:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3b62286d0ef785815994e2558e8cfb686597b0cd'/>
<id>urn:sha1:3b62286d0ef785815994e2558e8cfb686597b0cd</id>
<content type='text'>
Free Software Foundation mailing address has been moved in the past and some
of the addresses here are outdated. Remove them from file headers since the
COPYING file in the kernel sources includes it.

Signed-off-by: Jarkko Nikula &lt;jarkko.nikula@linux.intel.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>ioatdma: Adding write back descriptor error status support for ioatdma 3.3</title>
<updated>2013-04-15T17:16:15Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2013-04-10T23:44:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=75c6f0ab480657269b5014e0e457c7b18ba8597e'/>
<id>urn:sha1:75c6f0ab480657269b5014e0e457c7b18ba8597e</id>
<content type='text'>
v3.3 provides support for write back descriptor error status. This allows
reporting of errors in a descriptor field. In supporting this, certain
errors such as P/Q validation errors no longer halts the channel. The DMA
engine can continue to execute until the end of the chain and allow software
to report the "errors" up the stack. We are also going to mask those error
interrupts and handle them when the "chain" has completed at the end.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Acked-by: Dan Williams &lt;djbw@fb.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
<entry>
<title>ioatdma: Adding support for 16 src PQ ops and super extended descriptors</title>
<updated>2013-04-15T17:16:15Z</updated>
<author>
<name>Dave Jiang</name>
<email>dave.jiang@intel.com</email>
</author>
<published>2013-04-15T17:25:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7727eaa4490b7244934fe31f05e7329f30715267'/>
<id>urn:sha1:7727eaa4490b7244934fe31f05e7329f30715267</id>
<content type='text'>
v3.3 introduced 16 sources PQ operations. This also introduced super extended
descriptors to support the 16 srcs operations. This patch adds support for
the 16 sources ops and in turn adds the super extended descriptors for those
ops.

5 SED pools are created depending on the descriptor sizes. An SED can be a 64
bytes sized descriptor or larger and must be physically contiguous. A kmem
cache pool is created for allocating the software descriptor that manages the
hardware descriptor. The super extended descriptor will take place of extended
descriptor under certain operations and be "attached" to the op descriptor
during operation. This is a new feature for ioatdma v3.3.

Signed-off-by: Dave Jiang &lt;dave.jiang@intel.com&gt;
Acked-by: Dan Williams &lt;djbw@fb.com&gt;
Acked-by: Dan Williams &lt;djbw@fb.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
</entry>
</feed>
