linux-dev/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile, branch linus/master

drm/amd/display: Add DCN315 CLK_MGR

2022-02-18T19:07:00Z

Clk and SMU interfaces for DCN 3.1.5. Signed-off-by: Qingqing Zhuo Acked-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: Add DCN316 resource and SMU clock manager

2022-02-17T20:58:45Z

Add core DC implementation for DCN316. Reviewed-by: Charlene Liu Acked-by: Prike Liang Reviewed-by: Leo Li Signed-off-by: Hansen Dsouza Signed-off-by: Alex Deucher

drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN

2021-10-04T19:23:02Z

No need for a separate kconfig option at this point. Reviewed-by: Zhan Liu Signed-off-by: Alex Deucher

drm/amd/display: add cyan_skillfish display support

2021-10-04T19:22:57Z

[Why] add display related cyan_skillfish files in. makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag. v2: squash in clang fixes from Harry, Nathan v3: squash in missing CONFIG_DRM_AMD_DC check (Alex) Signed-off-by: Charlene Liu Signed-off-by: Zhan Liu Reviewed-by: Charlene Liu Acked-by: Jun Lei Acked-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN

2021-06-22T20:51:45Z

No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amd/display: Add DCN3.1 clock manager support

2021-06-04T20:03:26Z

Adds support for clock requests for the various parts of the DCN3.1 IP and the interfaces and definitions for sending messages to SMU/PMFW. Includes new support for z9/10, detecting SMU timeout and p-state support enablement. Acked-by: Huang Rui Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amdgpu/display: drop DCN support for aarch64

2021-01-06T21:24:10Z

From Ard: "Simply disabling -mgeneral-regs-only left and right is risky, given that the standard AArch64 ABI permits the use of FP/SIMD registers anywhere, and GCC is known to use SIMD registers for spilling, and may invent other uses of the FP/SIMD register file that have nothing to do with the floating point code in question. Note that putting kernel_neon_begin() and kernel_neon_end() around the code that does use FP is not sufficient here, the problem is in all the other code that may be emitted with references to SIMD registers in it. So the only way to do this properly is to put all floating point code in a separate compilation unit, and only compile that unit with -mgeneral-regs-only." Disable support until the code can be properly refactored to support this properly on aarch64. Acked-by: Will Deacon Reported-by: Ard Biesheuvel Signed-off-by: Alex Deucher

drm/amdgpu/display: FP fixes for DCN3.x (v4)

2020-11-04T22:11:43Z

Add proper FP_START/END handling and adjust Makefiles per previous asics. v2: fix up harder. v3: fix clkmgr Makefile for dcn30 v4: fix old gcc handling is only required for x86 Build-tested-by: Nathan Chancellor Reviewed-by: Harry Wentland (v1) Reviewed-by: Nicholas Kazlauskas (v1) Signed-off-by: Alex Deucher

drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)

2020-11-04T22:11:37Z

Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov (v1) Signed-off-by: Alex Deucher

drm/amd/display: Add dcn3.01 support to DC (v2)

2020-10-05T19:15:56Z

Update dc for vangogh support. v2: fix compilation without DCN 301 set. Signed-off-by: Roman Li Signed-off-by: Alex Deucher