linux-dev/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c, branch linus/master

drm/amd/display: revert "Reset fifo after enable otg"

2022-02-02T23:35:00Z

[Why] This change causes regression, that prevents some systems from lighting up internal displays. [How] Revert this patch until a new solution is ready. Tested-by: Daniel Wheeler Reviewed-by: Charlene Liu Acked-by: Stylon Wang Signed-off-by: Zhan Liu Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amd/display: Reset fifo after enable otg

2021-11-22T19:45:01Z

[Why] In fast boot sequence, when change dispclk, otg is disabled but digfe is enabled. This may cause dig fifo error. [How] Reset dig fifo after enable otg. Reviewed-by: Jun Lei Reviewed-by: Anthony Koo Acked-by: Wayne Lin Signed-off-by: JinZe.Xu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add PPS immediate update flag for DCN2

2021-09-28T13:30:12Z

[Why] This change is needed for DCN2 to make use of the immediate_update flag. With this flag, update to PPS will be immediate, rather than always taking place on dig_update signal. [How] Set AFMT_GENERIC7_FRAME/IMMEDIATE_UPDATE bits depending on flag value. Reviewed-by: Wenjing Liu Acked-by: Anson Jacob Signed-off-by: Ilya Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix issue with dynamic bpp change for DCN3x

2021-09-23T19:17:30Z

Why: Screen sometimes would have artifacts or blink once at the time when bpp is dynamically changed. How: 1. Changed to update PPS infopacket in frame mode instead of immediate mode since other updates for bpp change are double-buffered. 2. Changed double-buffering enablement programming for DCN30 as advised by ASIC team Reviewed-by: Wenjing Liu Acked-by: Rodrigo Siqueira Signed-off-by: Bing Guo Signed-off-by: Alex Deucher

drm/amd/display: Add DPCD writes at key points

2021-09-14T19:57:09Z

This reverts commit "Revert "Add DPCD writes at key points" ". The following patch will fix the system hang issue. v2: squash in indentation warning fix Signed-off-by: Leo (Hanghong) Ma Acked-by: Mikita Lipski Reviewed-by: Aric Cyr Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add interface to get Calibrated Avg Level from FIFO

2021-06-15T21:25:41Z

[WHY] Hardware has handed down a new sequence requiring the value of this register be read from clk_mgr. Signed-off-by: Wesley Chalmers Reviewed-by: Dmytro Laktyushkin Acked-by: Anson Jacob Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Rename set_mst_bandwidth to align with DP spec

2020-09-15T21:52:41Z

[Why] The function set_mst_bandwidth is poorly name since it isn't clear what it does, and it also does not reflect any part of the allocation sequence described in the DP spec. [How] Rename the function set_mst_bandwidth to set_throttled_vcp_size. Signed-off-by: George Shen Acked-by: Aurabindo Pillai Signed-off-by: Alex Deucher

drm/amd/display: Improve compatibility by re-ordering info-packets

2020-07-21T19:37:39Z

[why] On DCN20, Some features would not be activated when ALLM was turned on. TV seemed to activate only the latest info packet sent, and the ALLM info packet was sent after the VSIF info packet. The packet indices was also inconsistent between DCN10 and DCN20. [how] Change the packet indices of DCN20 to match those of DCN10. This makes them consistent and also makes the vendor info packet be sent after the hfvsif info packet. Signed-off-by: Naveed Ashfaq Reviewed-by: Anthony Koo Acked-by: Qingqing Zhuo Signed-off-by: Alex Deucher

drm/amd/display: add stream_enc_inst for PSP HDCP inst use

2020-02-06T20:04:37Z

[why] new HW engine mapping requirment use in PSP [how] report stream_enc_inst Signed-off-by: Charlene Liu Reviewed-by: Wenjing Liu Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher

drm/amd/display: Reset steer fifo before unblanking the stream

2019-12-05T21:29:51Z

[why] During mode transition steer fifo could overflow. Quite often it recovers by itself, but sometimes it doesn't. [how] Add steer fifo reset before unblanking the stream. Also add a short delay when resetting dig resync fifo to make sure register writes don't end up back-to-back, in which case the HW might miss the reset request. Signed-off-by: Nikola Cornij Reviewed-by: Tony Cheng Acked-by: Leo Li Signed-off-by: Alex Deucher