<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2021-12-13T21:32:34Z</updated>
<entry>
<title>drm/amd: append missing includes</title>
<updated>2021-12-13T21:32:34Z</updated>
<author>
<name>Isabella Basso</name>
<email>isabbasso@riseup.net</email>
</author>
<published>2021-12-08T01:25:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=64cf26f04ad05ac7b4fc7d3339d893f21a06cab1'/>
<id>urn:sha1:64cf26f04ad05ac7b4fc7d3339d893f21a06cab1</id>
<content type='text'>
This fixes warnings caused by global functions lacking prototypes:, such as:

 warning: no previous prototype for 'dcn303_hw_sequencer_construct'
 [-Wmissing-prototypes]
 12 | void dcn303_hw_sequencer_construct(struct dc *dc)
    |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 ...
 warning: no previous prototype for ‘amdgpu_has_atpx’
 [-Wmissing-prototypes]
 76 | bool amdgpu_has_atpx(void) {
    |      ^~~~~~~~~~~~~~~

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Isabella Basso &lt;isabbasso@riseup.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor visual confirm</title>
<updated>2021-06-08T16:18:37Z</updated>
<author>
<name>Wyatt Wood</name>
<email>wyatt.wood@amd.com</email>
</author>
<published>2021-05-06T20:11:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=60df84418c0a9dc1a40c1de8bb1be3676ee96f14'/>
<id>urn:sha1:60df84418c0a9dc1a40c1de8bb1be3676ee96f14</id>
<content type='text'>
[Why + How]
Visual confirm has no asic-specific logic,
so we can refactor and unify these functions
that are currently spread out across multiple
dcn files.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.
This will allow visual confirm to updated independently
of MPCC blending updates.

v2: squash in DCN3.1 fixes

Signed-off-by: Wyatt Wood &lt;wyatt.wood@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>Revert "drm/amd/display: Refactor and add visual confirm for HW Flip Queue"</title>
<updated>2021-05-27T16:26:45Z</updated>
<author>
<name>Qingqing Zhuo</name>
<email>qingqing.zhuo@amd.com</email>
</author>
<published>2021-05-20T18:58:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=eae902f95e4585a1e18625d5fed19cdf43e2267d'/>
<id>urn:sha1:eae902f95e4585a1e18625d5fed19cdf43e2267d</id>
<content type='text'>
This reverts commit 3ca402375a2197579d1029e7fa9d856847fe0e7b.

Recent visual confirm changes are regressing the driver, causing a
black screen on boot in some green sardine configs, or visual confirm
is not updated at all.

Signed-off-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor and add visual confirm for HW Flip Queue</title>
<updated>2021-05-20T02:39:36Z</updated>
<author>
<name>Wyatt Wood</name>
<email>wyatt.wood@amd.com</email>
</author>
<published>2021-05-06T20:11:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3ca402375a2197579d1029e7fa9d856847fe0e7b'/>
<id>urn:sha1:3ca402375a2197579d1029e7fa9d856847fe0e7b</id>
<content type='text'>
[Why]
Visual confirm will indicate if driver is programming
the surface address.
Refactor is required because much of the visual confirm
logic is buried deep in the mpcc files.
In addition, visual confirm is not updated during fast updates.

[How]
In order to have visual confirm for driver flips, visual confirm
needs to be updated on every frame, including fast updates.
Add a new hw sequencer interface update_visual_confirm_color,
and a new mpc function pointer set_bg_color.

v2: drop unused variable (Alex)

Signed-off-by: Wyatt Wood &lt;wyatt.wood@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add function and debugfs to dump DCC_EN bit</title>
<updated>2021-04-09T20:52:03Z</updated>
<author>
<name>Victor Lu</name>
<email>victorchengchi.lu@amd.com</email>
</author>
<published>2020-07-22T20:16:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=712343cd21ea709ba63869f74246466524172ad4'/>
<id>urn:sha1:712343cd21ea709ba63869f74246466524172ad4</id>
<content type='text'>
[why]
Currently to view the DCC_EN bit the entire DTN log
must be dumped. A compact method to view the DCC_EN
bit is desirable.

[how]
Introduce new debugfs interface that only dumps the
DCC_EN bit.

Example usage:
cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en

Signed-off-by: Victor Lu &lt;victorchengchi.lu@amd.com&gt;
Reviewed-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Old sequence for HUBP blank</title>
<updated>2021-02-18T21:43:11Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2021-02-04T13:21:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0b7421f0a6a41a8ce60c4dadf6f9e7c62fbd2f1f'/>
<id>urn:sha1:0b7421f0a6a41a8ce60c4dadf6f9e7c62fbd2f1f</id>
<content type='text'>
New proposed sequence for HUBP blanking causes regressions where the
hardware would fail to enter blank which triggers an assert in the new
sequence. This change brings back the old sequence.

Fixes: 985faf2c4ecb60 ("drm/amd/display: New sequence for HUBP blank")
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Bhawanpreet Lakha &lt;bhawanpreet.lakha@amd.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: New sequence for HUBP blank</title>
<updated>2021-01-14T04:44:22Z</updated>
<author>
<name>Wesley Chalmers</name>
<email>Wesley.Chalmers@amd.com</email>
</author>
<published>2020-12-07T16:53:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=985faf2c4ecb606552293a5af1f0b5f99b7b1a3d'/>
<id>urn:sha1:985faf2c4ecb606552293a5af1f0b5f99b7b1a3d</id>
<content type='text'>
[WHY]
DCN30 has a bug where blanking HUBP blocks pstate allow unless
HUBP_DISABLE is toggled afterwards.

[HOW]
Create a HW sequence for blanking HUBP.
1. Wait for enter VBLANK
2. Set HUBP_BLANK
3. Make sure HUBP_IN_BLANK = 1
4. Toggle HUBP_DISABLE on and off to perform soft reset

All existing calls to hubp-&gt;funcs-&gt;set_blank should be replaced with
this new sequence.
In wait_for_mpcc_disconnect, only blank the pipe being disconnected, and
leave all other pipes unmodified.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2</title>
<updated>2020-11-02T20:31:30Z</updated>
<author>
<name>Joshua Aberback</name>
<email>joshua.aberback@amd.com</email>
</author>
<published>2020-10-19T23:30:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=dbf5256bbf1949f0bffb37134660db03be14fd78'/>
<id>urn:sha1:dbf5256bbf1949f0bffb37134660db03be14fd78</id>
<content type='text'>
[Why]
Prior commit "Blank HUBP during pixel data blank for DCN30"
missed the call to set_disp_pattern_generator from
set_crtc_test_pattern, which re-exposed the issue for which
we initially blocked active-only p-state switching.

[How]
 - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version
 - new hwss funciton set_disp_pattern_generator
 - dcn20 version just calls opp_set_disp_pattern_generator
 - dcn30 version implements the HUBP blank

Signed-off-by: Joshua Aberback &lt;joshua.aberback@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Update GSL state if leaving immediate flip</title>
<updated>2020-10-26T17:33:24Z</updated>
<author>
<name>Alvin Lee</name>
<email>alvin.lee2@amd.com</email>
</author>
<published>2020-10-08T17:32:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=86c5a9e3aa66eeee663ead6104514ecdd9996925'/>
<id>urn:sha1:86c5a9e3aa66eeee663ead6104514ecdd9996925</id>
<content type='text'>
[Why]
We should leave GSL if we're not doing immediate flip no matter if
we're doing pipe split or not

[How]
Check for updating GSL state whenever we're not doing
immediate flip

v2: Squash in build fix (Alex)

Signed-off-by: Aric Cyr &lt;aric.cyr@amd.com&gt;
Signed-off-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Acked-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Block ABM in case of eDP ODM</title>
<updated>2020-10-05T19:16:43Z</updated>
<author>
<name>Yongqiang Sun</name>
<email>yongqiang.sun@amd.com</email>
</author>
<published>2020-09-18T20:33:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=54e8094a76bc8cd41d1ec5c2c2a8755e64349142'/>
<id>urn:sha1:54e8094a76bc8cd41d1ec5c2c2a8755e64349142</id>
<content type='text'>
[Why]
enable ODM on eDP panel with ABM will result in color difference
on the panel due to only one ABM module to set one pipe.

[How]
Block ABM in case of ODM enabled on eDP.

Signed-off-by: Yongqiang Sun &lt;yongqiang.sun@amd.com&gt;
Reviewed-by: Eric Yang &lt;eric.yang2@amd.com&gt;
Acked-by: Eryk Brol &lt;eryk.brol@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
