<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/display/dc/dcn302, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn302?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn302?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-05-26T18:56:31Z</updated>
<entry>
<title>drm/amd/display: Move FPU associated DCN30 code to DML folder</title>
<updated>2022-05-26T18:56:31Z</updated>
<author>
<name>Jasdeep Dhillon</name>
<email>jdhillon@amd.com</email>
</author>
<published>2022-05-06T17:03:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e4b0eac3e6242abf5f5ebcffdeb852e7ffa1c3d0'/>
<id>urn:sha1:e4b0eac3e6242abf5f5ebcffdeb852e7ffa1c3d0</id>
<content type='text'>
[why &amp; how]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN30 to DML, where all FPU code
should locate.

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable 3 plane for DCN 3.0 and 3.02</title>
<updated>2022-04-05T14:29:48Z</updated>
<author>
<name>Krunoslav Kovac</name>
<email>Krunoslav.Kovac@amd.com</email>
</author>
<published>2022-03-25T18:41:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0191d384176c00fa28b52393997c61fce346564f'/>
<id>urn:sha1:0191d384176c00fa28b52393997c61fce346564f</id>
<content type='text'>
[WHY&amp;HOW]
Increase num of bottom planes to 2. Note that DCN 3.03 is left out
since it has max 2 planes.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Tom Chung &lt;chiahsuan.chung@amd.com&gt;
Signed-off-by: Krunoslav Kovac &lt;Krunoslav.Kovac@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: move dpcs_3_0_0 headers from dcn to dpcs</title>
<updated>2022-02-07T23:03:50Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2022-02-03T17:52:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=68550cbc6129159b7a6434796b721e8b66ee12f6'/>
<id>urn:sha1:68550cbc6129159b7a6434796b721e8b66ee12f6</id>
<content type='text'>
To align with other headers.

Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: move FPU associated DCN302 code to DML folder (#2266)</title>
<updated>2022-01-18T22:42:26Z</updated>
<author>
<name>Jasdeep Dhillon</name>
<email>jdhillon@amd.com</email>
</author>
<published>2022-01-05T20:59:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f369e4eba89a6fc1cac619db86c00a964d1fc0a2'/>
<id>urn:sha1:f369e4eba89a6fc1cac619db86c00a964d1fc0a2</id>
<content type='text'>
[Why &amp; How]
As part of the FPU isolation work documented in
https://patchwork.freedesktop.org/series/93042/, isolate
code that uses FPU in DCN302 to DML, where all FPU code
should locate.

Co-authored-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Changed pipe split policy to allow for multi-display pipe split</title>
<updated>2021-12-30T13:54:44Z</updated>
<author>
<name>Angus Wang</name>
<email>angus.wang@amd.com</email>
</author>
<published>2021-12-09T22:27:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=458c79a86ae1081636942ba3c42bf0424f3c6970'/>
<id>urn:sha1:458c79a86ae1081636942ba3c42bf0424f3c6970</id>
<content type='text'>
[WHY]
Current implementation of pipe split policy prevents pipe split with
multiple displays connected, which caused the MCLK speed to be stuck at
max

[HOW]
Changed the pipe split policies so that pipe split is allowed for
multi-display configurations

Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1522
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1709
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1655
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1403

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Angus Wang &lt;angus.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd: append missing includes</title>
<updated>2021-12-13T21:32:34Z</updated>
<author>
<name>Isabella Basso</name>
<email>isabbasso@riseup.net</email>
</author>
<published>2021-12-08T01:25:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=64cf26f04ad05ac7b4fc7d3339d893f21a06cab1'/>
<id>urn:sha1:64cf26f04ad05ac7b4fc7d3339d893f21a06cab1</id>
<content type='text'>
This fixes warnings caused by global functions lacking prototypes:, such as:

 warning: no previous prototype for 'dcn303_hw_sequencer_construct'
 [-Wmissing-prototypes]
 12 | void dcn303_hw_sequencer_construct(struct dc *dc)
    |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 ...
 warning: no previous prototype for ‘amdgpu_has_atpx’
 [-Wmissing-prototypes]
 76 | bool amdgpu_has_atpx(void) {
    |      ^~~~~~~~~~~~~~~

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Isabella Basso &lt;isabbasso@riseup.net&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Enable P010 for DCN3x ASICs</title>
<updated>2021-12-01T21:04:56Z</updated>
<author>
<name>Stylon Wang</name>
<email>stylon.wang@amd.com</email>
</author>
<published>2021-11-12T12:05:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ebe5ffd8e271e328f33c4bc5cb8cea2b4cf8e058'/>
<id>urn:sha1:ebe5ffd8e271e328f33c4bc5cb8cea2b4cf8e058</id>
<content type='text'>
[Why + How]
Enable P010 for SDR video applications.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Reviewed-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Acked-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix LTTPR not Enabled</title>
<updated>2021-11-22T19:45:01Z</updated>
<author>
<name>Angus Wang</name>
<email>angus.wang@amd.com</email>
</author>
<published>2021-11-12T17:13:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2430be71c0176ef2757b63df5a25aa5c9e488e25'/>
<id>urn:sha1:2430be71c0176ef2757b63df5a25aa5c9e488e25</id>
<content type='text'>
[WHY]
Previous LTTPR change has caused a regression that led to an
issue where LTTPR is disabled

[HOW]
Extended changes from previous fix to DCN30X

Reviewed-by: Wesley Chalmers &lt;wesley.chalmers@amd.com&gt;
Reviewed-by: Martin Leung &lt;Martin.Leung@amd.com&gt;
Reviewed-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Angus Wang &lt;angus.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Revert changes for MPO underflow</title>
<updated>2021-11-22T19:45:01Z</updated>
<author>
<name>Angus Wang</name>
<email>angus.wang@amd.com</email>
</author>
<published>2021-11-03T15:54:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=fd3b2e21b8816273ca7813a8c9455c41ff77a96a'/>
<id>urn:sha1:fd3b2e21b8816273ca7813a8c9455c41ff77a96a</id>
<content type='text'>
[WHY]
The previous changes for fixing MPO underflow with multiple
display connected caused a regression where the machine runs
into a hang when doing multiple driver pnp with multiple displays
connected

[HOW]
Reverted offending change

Reviewed-by: Martin Leung &lt;Martin.Leung@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Angus Wang &lt;angus.wang@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix RGB MPO underflow with multiple displays</title>
<updated>2021-11-17T21:58:06Z</updated>
<author>
<name>Angus Wang</name>
<email>angus.wang@amd.com</email>
</author>
<published>2021-11-04T20:51:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=80c5f69b94249dc1e0a600cbef3cc055ea432af9'/>
<id>urn:sha1:80c5f69b94249dc1e0a600cbef3cc055ea432af9</id>
<content type='text'>
[WHY]
With RGB MPO enabled, playing a video with multiple displays connected
results in underflow when closing the video window

[HOW]
Reverted the old change to fix this problem, which prevented pipe splits
for multiple display configurations and caused high MCLK speeds during
idle. Added a two step call to dc_update_planes_and_stream, first time
with pipe split disabled and the second time with pipe split enabled,
which fixed the underflow issue

Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Anson Jacob &lt;Anson.Jacob@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Angus Wang &lt;angus.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
