linux-dev/drivers/gpu/drm/amd/display/dc/dcn30, branch linus/master

drm/amd/display: Move FPU associated DCN30 code to DML folder

2022-05-26T18:56:31Z

[why & how] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN30 to DML, where all FPU code should locate. Reviewed-by: Rodrigo Siqueira Acked-by: Qingqing Zhuo Signed-off-by: Jasdeep Dhillon Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Remove outdated register for dcn3+

2022-05-04T14:43:55Z

[Why & How] Remove MPCC_OGAM_LUT_RAM_CONTROL register which is outdated. Reviewed-by: Nevenko Stupar Reviewed-by: Martin Leung Acked-by: Wayne Lin Signed-off-by: Tse Kaitlyn Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Make OPTC3 function accessible to other DCN

2022-05-04T14:43:55Z

[Why] Newer DCN should use optc3 [How] Declare optc3 vmin/vmax function in header. Reviewed-by: Harry Vanzylldejong Acked-by: Wayne Lin Signed-off-by: Alvin Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add Audio readback registers

2022-04-25T21:10:17Z

[Why] Can be useful for verifying the correctness of audio output. Reviewed-by: Aric Cyr Acked-by: Tom Chung Signed-off-by: Ilya Bakoulin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: add DCN30 support FEC init

2022-04-12T18:19:15Z

[Why] FEC init used on DCN30. [How] Check fec active when HW init. Co-authored-by: Jingwen Zhu Reviewed-by: Wenjing Liu Acked-by: Pavle Kotarac Signed-off-by: Jingwen Zhu Signed-off-by: Alex Deucher

drm/amd/display: Enable 3 plane for DCN 3.0 and 3.02

2022-04-05T14:29:48Z

[WHY&HOW] Increase num of bottom planes to 2. Note that DCN 3.03 is left out since it has max 2 planes. Tested-by: Daniel Wheeler Reviewed-by: Aric Cyr Acked-by: Tom Chung Signed-off-by: Krunoslav Kovac Signed-off-by: Alex Deucher

drm/amd/display: Enable power gating before init_pipes

2022-04-01T03:05:53Z

[Why] In init_hw() we call init_pipes() before enabling power gating. init_pipes() tries to power gate dsc but it may fail because required force-ons are not released yet. As a result with dsc config the following errors observed on resume: "REG_WAIT timeout 1us * 1000 tries - dcn20_dsc_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_dpp_pg_control" "REG_WAIT timeout 1us * 1000 tries - dcn20_hubp_pg_control" [How] Move enable_power_gating_plane() before init_pipes() in init_hw() Reviewed-by: Anthony Koo Reviewed-by: Eric Yang Acked-by: Alex Hung Signed-off-by: Roman Li Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add pstate verification and recovery for DCN31

2022-03-15T18:33:57Z

[Why] To debug when p-state is being blocked and avoid PMFW hangs when it does occur. [How] Re-use the DCN10 hardware sequencer by adding a new interface for verifying p-state high on the hubbub. The interface is mostly the same as the DCN10 interface, but the bit definitions have changed for the debug bus. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Eric Yang Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher

drm/amd/display: move FPU-related code from dcn20 to dml folder

2022-03-15T18:25:16Z

Move parts of dcn20 code that uses FPU to dml folder. It aims to isolate FPU operations as described by series: drm/amd/display: Introduce FPU directory inside DC https://patchwork.freedesktop.org/series/93042/ This patch moves the following functions from dcn20_resource to dml/dcn20_fpu and calls of public functions in dcn20_resource are wrapped by DC_FP_START/END(): - void dcn20_populate_dml_writeback_from_context - static bool is_dtbclk_required() - static enum dcn_zstate_support_state() - void dcn20_calculate_dlg_params() - static void swizzle_to_dml_params() - int dcn20_populate_dml_pipes_from_context() - void dcn20_calculate_wm() - void dcn20_cap_soc_clocks() - void dcn20_update_bounding_box() - void dcn20_patch_bounding_box() - bool dcn20_validate_bandwidth_fp() This movement also affects dcn21/30/31, as dcn20_calculate_dlg_params() is used by them. For this reason, I included dcn20_fpu headers in dcn20_resource headers to make dcn20_calculate_dlg_params() visible to dcn21/30/31. Three new functions are created to isolate well-delimited FPU operations: - void dcn20_fpu_set_wb_arb_params(): set cli_watermark, pstate_watermark and time_per_pixel from wb_arb_params (struct mcif_arb_params), since those uses FPU operations on double types: WritebackUrgentWatermark, WritebackDRAMClockChangeWatermark, '16.0'. - void dcn20_fpu_set_wm_ranges(): set min_fill_clk_mhz and max_fill_clk_mhz involves FPU calcs on dram_speed_mts (double type); - void dcn20_fpu_adjust_dppclk(): adjust operation on RequiredDPPCLK that is a double. Signed-off-by: Melissa Wen Acked-by: Alan Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: add gamut coefficient set A and B

2022-03-15T18:25:15Z

[Why] Screen shake on DCN3 night light SDR BR3. [How] Change the logic to use double buffer reisgter on gamut settings. Reviewed-by: Krunoslav Kovac Acked-by: Alan Liu Signed-off-by: Jingwen Zhu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher