<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/display/dc/dcn30, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn30?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn30?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-10-10T21:32:55Z</updated>
<entry>
<title>drm/amd/display: Use set_vtotal_min_max to configure OTG VTOTAL</title>
<updated>2022-10-10T21:32:55Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2021-03-12T16:58:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=15e8b368981e1e8420f08b35bb12b794b200f4a0'/>
<id>urn:sha1:15e8b368981e1e8420f08b35bb12b794b200f4a0</id>
<content type='text'>
In multiple parts of the DCN code, we write directly to the
OTG_V_TOTAL_* registers in some OPTC functions. Let's avoid it by using
the set_vtotal_min_max.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Use the same cursor info across features</title>
<updated>2022-10-10T21:32:55Z</updated>
<author>
<name>Max Tseng</name>
<email>Max.Tseng@amd.com</email>
</author>
<published>2022-10-02T12:45:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b73353f7f3d434e90da9f0e127bba1fe26cb1287'/>
<id>urn:sha1:b73353f7f3d434e90da9f0e127bba1fe26cb1287</id>
<content type='text'>
Since different features would need to update cursor registers, However,
they would use different approaches.

To unify varied methods, this refactor is implemented the same update
cursor info method for current varied features.

Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Max Tseng &lt;Max.Tseng@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Remove OPTC lock check</title>
<updated>2022-10-06T16:02:04Z</updated>
<author>
<name>Rodrigo Siqueira</name>
<email>Rodrigo.Siqueira@amd.com</email>
</author>
<published>2022-09-21T12:47:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b33cd65df18f1cf60b066a02c09df92b4763bb31'/>
<id>urn:sha1:b33cd65df18f1cf60b066a02c09df92b4763bb31</id>
<content type='text'>
At some point, we decided to blank HUBP during pixel data blank, and to
handle that, we added some OPTC lock checks. Later, we realized that
this change caused multiple regression, and we removed it. Nevertheless,
we still have some leftovers that might affect some ASIC behavior, and
this commit drops those changes to keep the code consistent.

Reviewed-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Signed-off-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add dummy pstate workaround to dcn315</title>
<updated>2022-10-06T16:00:32Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2022-09-16T19:55:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4931ce22eca6ed5f8a3a3820fd13e586011ac219'/>
<id>urn:sha1:4931ce22eca6ed5f8a3a3820fd13e586011ac219</id>
<content type='text'>
DCN315 has to always allow pstate change or SMU will hang. This
workaround achieves this by applying a low pstate change latency
to be used when pstate is calculated to be unsupported. This lower
latency only accounts for memory retraining; a previous change
handles locking in the highest available pstate allowing us to minimize
required latency hiding to only account for memory retraining.

Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add debug option for exiting idle optimizations on cursor updates</title>
<updated>2022-09-29T13:41:44Z</updated>
<author>
<name>Brandon Syu</name>
<email>Brandon.Syu@amd.com</email>
</author>
<published>2022-09-15T10:16:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=936675464b1f481ad432d6a4fb75405c0abc71c7'/>
<id>urn:sha1:936675464b1f481ad432d6a4fb75405c0abc71c7</id>
<content type='text'>
[Description]
- Have option to exit idle opt on cursor updates
for debug and optimizations purposes

Reviewed-by: Aric Cyr &lt;Aric.Cyr@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Brandon Syu&lt;Brandon.Syu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: do not compare integers of different widths</title>
<updated>2022-09-19T19:15:30Z</updated>
<author>
<name>Josip Pavic</name>
<email>Josip.Pavic@amd.com</email>
</author>
<published>2022-09-08T16:01:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ca86bbdd9b47464d78ae6af565a6e78c6e4e2fbd'/>
<id>urn:sha1:ca86bbdd9b47464d78ae6af565a6e78c6e4e2fbd</id>
<content type='text'>
[Why &amp; How]
Increase width of some variables to avoid comparing integers of
different widths

Reviewed-by: Alvin Lee &lt;alvin.lee2@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Josip Pavic &lt;Josip.Pavic@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Disable SubVP on driver disable</title>
<updated>2022-09-19T19:12:44Z</updated>
<author>
<name>Alvin Lee</name>
<email>Alvin.Lee2@amd.com</email>
</author>
<published>2022-09-01T23:03:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b0f5b1004ef8fbdd7cb314fe0bbbc115beae057a'/>
<id>urn:sha1:b0f5b1004ef8fbdd7cb314fe0bbbc115beae057a</id>
<content type='text'>
[Why and How]
- For driver disable cases in current implementation, if P-State
  is unsupported or still supported by firmware, we force it
  supported by DCN.

- SubVP now needs to be included in this case along with FPO.

Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Alvin Lee &lt;Alvin.Lee2@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: rework recent update PHY state commit</title>
<updated>2022-09-19T19:10:24Z</updated>
<author>
<name>Wenjing Liu</name>
<email>wenjing.liu@amd.com</email>
</author>
<published>2022-08-31T18:56:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9c75891feef0f9f67cf1c8f8038371006e25d23f'/>
<id>urn:sha1:9c75891feef0f9f67cf1c8f8038371006e25d23f</id>
<content type='text'>
[why]
Original change 594b237b9a07 ("drm/amd/display: Add
interface to track PHY state") was implemented by assuming stream's
dpms off is equivalent to PHY power off.
This assumption doesn't hold in following situations:
1. MST multiple stream scenario, where multiple streams are sharing the
same PHY output. Toggle dpms off for one of the stream doesn't power
off the PHY due to the presence of other streams.
2. enable stream failure scenario, where enable stream fails due to
failure of link training. This will cause DPMS off is set to false, while
the actual PHY power state is off in certain cases.
Due to the problematic assumption, the logic will skip disabling
other streams for MST multiple stream scenario, therefore PHY is
not actually powered off.

[how]
1. Rework this refactor by moving PHY state update down to hardware
level, where we update PHY state in place when hardware sequencer
is actually changing the power state of the PHY hardware.
2. Reimplement symclk on TX off workaround in place when we are actually
calling transmitter control to power off PHY in dcn32. Note the workaround is
added due to the lack of proper software interface to set TX while keeping
symclk on. We plan to address this interface problem so we can set TX off
only without affecting symclk in future dcn versions.

Fixes: 594b237b9a07 ("drm/amd/display: Add interface to track PHY state")
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Wenjing Liu &lt;wenjing.liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: make some functions static</title>
<updated>2022-09-14T16:38:52Z</updated>
<author>
<name>Jiapeng Chong</name>
<email>jiapeng.chong@linux.alibaba.com</email>
</author>
<published>2022-09-14T05:27:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e0f1d483b85bd35ed10985e7d3e64386e4e14e50'/>
<id>urn:sha1:e0f1d483b85bd35ed10985e7d3e64386e4e14e50</id>
<content type='text'>
These functions are not used outside the file dcn30_resource.c, so the
modification is defined as static.

drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1949:6: warning: no previous prototype for ‘is_refresh_rate_support_mclk_switch_using_fw_based_vblank_stretch’.
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_resource.c:1919:5: warning: no previous prototype for ‘get_frame_rate_at_max_stretch_100hz’.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2143
Reported-by: Abaci Robot &lt;abaci@linux.alibaba.com&gt;
Signed-off-by: Jiapeng Chong &lt;jiapeng.chong@linux.alibaba.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: update header files</title>
<updated>2022-09-13T16:56:08Z</updated>
<author>
<name>Charlene Liu</name>
<email>Charlene.Liu@amd.com</email>
</author>
<published>2022-08-23T13:39:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9dea5dd0e9dc65c9f5fd9390062381b17ef242b2'/>
<id>urn:sha1:9dea5dd0e9dc65c9f5fd9390062381b17ef242b2</id>
<content type='text'>
[why]
update header files, and remove not used register access marco

Reviewed-by: Hansen Dsouza &lt;hansen.dsouza@amd.com&gt;
Acked-by: Pavle Kotarac &lt;Pavle.Kotarac@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
