<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/display/dc/dcn314, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn314?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dcn314?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-11-09T23:01:59Z</updated>
<entry>
<title>drm/amd/display: Fix reg timeout in enc314_enable_fifo</title>
<updated>2022-11-09T23:01:59Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2022-10-27T19:34:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ce62198d8b62734a985d22652e75a649be052390'/>
<id>urn:sha1:ce62198d8b62734a985d22652e75a649be052390</id>
<content type='text'>
[Why]
The link enablement sequence can end up resetting the encoder while
the PHY symclk isn't yet on.

This means that waiting for symclk on will timeout, along with the reset
bit never asserting high.

This causes unnecessary delay when enabling the link and produces a
warning affecting multiple IGT tests.

[How]
Don't wait for the symclk to be on here because firmware already does.

Don't wait for reset if we know the symclk isn't on.

Split the reset into a helper function that checks the bit and decides
whether or not a delay is sufficient.

Reviewed-by: Roman Li &lt;Roman.Li@amd.com&gt;
Acked-by: Alan Liu &lt;HaoPing.Liu@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.0.x
</content>
</entry>
<entry>
<title>drm/amd/display: Update DSC capabilitie for DCN314</title>
<updated>2022-11-02T20:45:42Z</updated>
<author>
<name>Leo Chen</name>
<email>sancchen@amd.com</email>
</author>
<published>2022-10-20T15:46:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=341421084d705475817f7f0d68e130370d10b20d'/>
<id>urn:sha1:341421084d705475817f7f0d68e130370d10b20d</id>
<content type='text'>
dcn314 has 4 DSC - conflicted hardware document updated and confirmed.

Tested-by: Mark Broadworth &lt;mark.broadworth@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Leo Chen &lt;sancchen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.0.x
</content>
</entry>
<entry>
<title>drm/amd/display: Update PMFW z-state interface for DCN314</title>
<updated>2022-10-10T21:11:41Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2022-09-09T19:24:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4f5bdde386d3b8e9317df5562950e1b4fa177599'/>
<id>urn:sha1:4f5bdde386d3b8e9317df5562950e1b4fa177599</id>
<content type='text'>
[Why]
Request from PMFW to change the messaging format to specify whether we
support z-state via individual bits.

[How]
Update the args we pass in the support message.

Fixes: d5c6909e7460 ("drm/amd/display: Add DCN314 clock manager")
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Reviewed-by: Mario Limonciello &lt;mario.limonciello@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Cc: stable@vger.kernel.org # 6.0
</content>
</entry>
<entry>
<title>drm/amd/display: Refactor edp ILR caps codes</title>
<updated>2022-10-06T16:00:02Z</updated>
<author>
<name>Ian Chen</name>
<email>ian.chen@amd.com</email>
</author>
<published>2022-08-23T09:26:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=1178ac68dc2869a2f4192600b701de3d853272d2'/>
<id>urn:sha1:1178ac68dc2869a2f4192600b701de3d853272d2</id>
<content type='text'>
We split out ILR config from "global" to "per-panel" config settings.

Reviewed-by: Anthony Koo &lt;Anthony.Koo@amd.com&gt;
Acked-by: Hamza Mahfooz &lt;hamza.mahfooz@amd.com&gt;
Signed-off-by: Ian Chen &lt;ian.chen@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: change to enc314_stream_encoder_dp_blank static</title>
<updated>2022-10-06T15:55:36Z</updated>
<author>
<name>Yang Yingliang</name>
<email>yangyingliang@huawei.com</email>
</author>
<published>2022-09-29T09:02:00Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d37f379ad04dcc21ebd1d2380c3bc979d54f7c46'/>
<id>urn:sha1:d37f379ad04dcc21ebd1d2380c3bc979d54f7c46</id>
<content type='text'>
enc314_stream_encoder_dp_blank is only used in dcn314_dio_stream_encoder.c now,
change it to static.

Fixes: c55bf690fe79 ("drm/amd/display: Add explicit FIFO disable for DP blank")
Signed-off-by: Yang Yingliang &lt;yangyingliang@huawei.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Fix typo in get_pixel_rate_div</title>
<updated>2022-09-29T13:41:45Z</updated>
<author>
<name>Taimur Hassan</name>
<email>Syed.Hassan@amd.com</email>
</author>
<published>2022-09-14T20:25:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c02e6444117f112bea468d3615ad6293cc7de64e'/>
<id>urn:sha1:c02e6444117f112bea468d3615ad6293cc7de64e</id>
<content type='text'>
[Why &amp; How]
Some FIFO errors still occur due to reading wrong pixel rate divider.
Fix typo to prevent FIFO error.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Taimur Hassan &lt;Syed.Hassan@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add explicit FIFO disable for DP blank</title>
<updated>2022-09-29T13:41:44Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2022-09-08T15:11:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c55bf690fe79f04cb8ebfe34144079777021cd7c'/>
<id>urn:sha1:c55bf690fe79f04cb8ebfe34144079777021cd7c</id>
<content type='text'>
[Why]
We rely on DMCUB to do this when disabling the link but it should
actually come before we disable the DP VID stream.

If we don't then the FIFO can end up with underflow that persists
the next time it's enabled.

[How]
Add a DCN314 specific blank sequence that will disable the DIG FIFO
first.

Reviewed-by: Syed Hassan &lt;Syed.Hassan@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Do DIO FIFO enable after DP video stream enable</title>
<updated>2022-09-29T13:41:44Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2022-09-07T14:11:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d3d61281edc0ab0c3d566e760d5bd4db5a9c217a'/>
<id>urn:sha1:d3d61281edc0ab0c3d566e760d5bd4db5a9c217a</id>
<content type='text'>
[Why]
Avoids a race condition where DIO FIFO can underflow due to no incoming
data available.

[How]
Shift the FIFO enable below stream enable.

Make sure fullness level is written before the DIO reset takes place
and that we're not doing it twice.

Reviewed-by: Syed Hassan &lt;Syed.Hassan@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Avoid avoid unnecessary pixel rate divider programming</title>
<updated>2022-09-29T13:41:44Z</updated>
<author>
<name>Taimur Hassan</name>
<email>Syed.Hassan@amd.com</email>
</author>
<published>2022-09-13T20:04:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=202c1e3dbc882c9040208223c12d158286475084'/>
<id>urn:sha1:202c1e3dbc882c9040208223c12d158286475084</id>
<content type='text'>
[Why]
Programming pixel rate divider when FIFO is enabled can cause FIFO error.

[How]
Skip divider programming when divider values are the same to prevent FIFO
error.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Jasdeep Dhillon &lt;jdhillon@amd.com&gt;
Signed-off-by: Taimur Hassan &lt;Syed.Hassan@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: correct num_dsc based on HW cap</title>
<updated>2022-09-19T19:17:03Z</updated>
<author>
<name>Charlene Liu</name>
<email>Charlene.Liu@amd.com</email>
</author>
<published>2022-09-10T19:08:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c09a9bee6459eb6976b6db3f33d2776243760d3f'/>
<id>urn:sha1:c09a9bee6459eb6976b6db3f33d2776243760d3f</id>
<content type='text'>
[why]
num_dsc is 3 for dcn314 based on HW capablity.

Reviewed-by: Martin Leung &lt;Martin.Leung@amd.com&gt;
Acked-by: Wayne Lin &lt;wayne.lin@amd.com&gt;
Signed-off-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
