linux-dev/drivers/gpu/drm/amd/display/dc/dcn32, branch master

drm/amd/display: Enforce minimum prefetch time for low memclk on DCN32

2022-11-09T23:04:13Z

[WHY?] Data return times when using lowest memclk can be <= 60us, which can cause underflow on high bandwidth displays with a workload. [HOW?] Enforce a minimum prefetch time during validation for low memclk modes. Reviewed-by: Jun Lei Acked-by: Alan Liu Signed-off-by: Dillon Varone Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Don't return false if no stream

2022-10-24T18:44:03Z

pipe_ctx[i] exists even if the pipe is not in use. If the pipe is not in use it will always have a null stream, so don't return false in this case. Tested-by: Daniel Wheeler Reviewed-by: Rodrigo Siqueira Acked-by: Qingqing Zhuo Signed-off-by: Alvin Lee Signed-off-by: Alex Deucher

drm/amd/display: Add HUBP surface flip interrupt handler

2022-10-12T15:27:41Z

Add the hubp surface flip handler. This fixes some flip timeout issues. Acked-by: Alex Deucher Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org # 6.0.x

drm/amd/display: Simplify bool conversion

2022-10-11T15:58:42Z

The result of 'pwr_status == 0' is Boolean, and the question mark expression is redundant. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2354 Reported-by: Abaci Robot Reviewed-by: Harry Wentland Signed-off-by: Yang Li Signed-off-by: Alex Deucher

drm/amd/display: Clean some DCN32 macros

2022-10-11T15:05:46Z

Some unused macros might mislead developers during the debug, which can be removed without any issue. This commit drops some unused references to SE_COMMON_MASK_SH_LIST_DCN32. Tested-by: Daniel Wheeler Acked-by: Qingqing Zhuo Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: increase hardware status wait time

2022-10-10T21:17:48Z

[Why] Diagnostics reports exceptions generated when timeout waiting for DISPCLK frequency divider change expires when testing ODM4to1. Diagnostics reports exceptions generated when timeout waiting for OTG busy status expires when disabling OTG during ODM4to1 test. [How] Increase HW status waiting time for DISPCLK frequency divider change and OTG busy status when disable OTG. Tested-by: Daniel Wheeler Reviewed-by: Ariel Bernstein Acked-by: Qingqing Zhuo Signed-off-by: Vladimir Stempen Signed-off-by: Alex Deucher

drm/amd/display: do not compare integers of different widths

2022-10-10T21:17:30Z

[Why & How] Increase width of some variables to avoid comparing integers of different widths Reviewed-by: Alvin Lee Tested-by: Daniel Wheeler Acked-by: Qingqing Zhuo Signed-off-by: Josip Pavic Signed-off-by: Alex Deucher

drm/amd/display: properly configure DCFCLK when enable/disable Freesync

2022-10-10T21:14:46Z

[Why] Bandwidth validation is using Freesync parameters from previous Freesync state. Bandwidth validation ignores DCFCLK calculated after Freesync parameters are configured [How] Set Freesync bandwidth parameters to its default state before running bandwidth validation. Take DCFCLK calculated after Freesync bandwidth parameters are assigned and bandwidth is recalculated. Tested-by: Daniel Wheeler Reviewed-by: Martin Leung Reviewed-by: Nevenko Stupar Reviewed-by: Jun Lei Acked-by: Qingqing Zhuo Signed-off-by: Vladimir Stempen Signed-off-by: Alex Deucher

drm/amd/display: Disconnect DSC for unused pipes during ODM transition

2022-10-06T16:04:15Z

[Why] During transition from ODM combine to ODM bypass, if DSC is enabled need to disconnect the DSC mux for pipes no longer in use. [How] During ODM update, detect pipes with DSC that are no longer being used for new state and call new DSC interface to disconnect. Add new DSC interface to disconnect from pipe Reviewed-by: Alvin Lee Signed-off-by: Rodrigo Siqueira Signed-off-by: Alex Deucher

drm/amd/display: unblock mcm_luts

2022-10-06T16:04:05Z

why and how: needed to fix bad assumption for enable mcm_luts Reviewed-by: Rodrigo Siqueira Signed-off-by: Martin Leung Signed-off-by: Alex Deucher