<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-03-25T16:40:25Z</updated>
<entry>
<title>drm/amd/display: Add support for zstate during extended vblank</title>
<updated>2022-03-25T16:40:25Z</updated>
<author>
<name>Gabe Teeger</name>
<email>gabe.teeger@amd.com</email>
</author>
<published>2022-03-14T16:07:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e5fc78252ccd8dfc260f87d83905e9dffff6d975'/>
<id>urn:sha1:e5fc78252ccd8dfc260f87d83905e9dffff6d975</id>
<content type='text'>
[why]
When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank
portion to enter zstate if possible.

[how]
When we enter freesync, a full update is triggered and the new vtotal
with extra lines is passed to dml in a stream update. The time gained
from extra vblank lines is calculated in microseconds. We allow zstate
entry if the time gained is greater than 5 ms, which is the current
policy. Furthermore, an optimized value for min_dst_y_next_start is
calculated and written to its register. When exiting freesync, another
full update is triggered and default values are restored.

Reviewed-by: Nicholas Kazlauskas &lt;Nicholas.Kazlauskas@amd.com&gt;
Acked-by: Alex Hung &lt;alex.hung@amd.com&gt;
Signed-off-by: Gabe Teeger &lt;gabe.teeger@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Set compbuf size to min at prep prevent overbook crb</title>
<updated>2022-02-23T19:21:43Z</updated>
<author>
<name>Duncan Ma</name>
<email>duncanma@amd.com</email>
</author>
<published>2022-02-08T20:05:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2e6e14c9e47dac61e341d4b8128184e3e0eb3568'/>
<id>urn:sha1:2e6e14c9e47dac61e341d4b8128184e3e0eb3568</id>
<content type='text'>
[Why]
Detbuffer size is dynamically set for dcn31x. At certain moment,
compbuf+(def size * num pipes) &gt; config return buffer size causing
flickering. This is easily reproducible when MPO is
enabled with two displays.

[How]
At prepare BW, use the min comp buffer size. When it is to
optimize BW, set compbuf size back to maximum possible size.

Reviewed-by: Charlene Liu &lt;Charlene.Liu@amd.com&gt;
Acked-by: Solomon Chiu &lt;solomon.chiu@amd.com&gt;
Signed-off-by: Duncan Ma &lt;duncanma@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: Remove t_srx_delay_us.</title>
<updated>2022-01-25T22:54:23Z</updated>
<author>
<name>Bas Nieuwenhuizen</name>
<email>bas@basnieuwenhuizen.nl</email>
</author>
<published>2022-01-23T02:38:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2a807341ed1074ab83638f2fab08dffaa373f6b8'/>
<id>urn:sha1:2a807341ed1074ab83638f2fab08dffaa373f6b8</id>
<content type='text'>
Unused. Convert the divisions into asserts on the divisor, to
debug why it is zero. The divide by zero is suspected of causing
kernel panics.

While I have no idea where the zero is coming from I think this
patch is a positive either way.

Cc: stable@vger.kernel.org
Reviewed-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Signed-off-by: Bas Nieuwenhuizen &lt;bas@basnieuwenhuizen.nl&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: log additional register state for debug</title>
<updated>2021-07-21T17:39:25Z</updated>
<author>
<name>Josip Pavic</name>
<email>Josip.Pavic@amd.com</email>
</author>
<published>2021-06-21T16:17:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=98e95e4f7996a60ee44ca6d8ab7f280e4bf7d618'/>
<id>urn:sha1:98e95e4f7996a60ee44ca6d8ab7f280e4bf7d618</id>
<content type='text'>
[Why &amp; How]
Extend existing state collection functions to add some additional
registers useful for debug, and add state collection function for DC
hubbub

Acked-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Signed-off-by: Josip Pavic &lt;Josip.Pavic@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN</title>
<updated>2021-06-22T20:51:45Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-06-21T20:51:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8fe44c080a53ac0ccbe88053a2e40f9acca33091'/>
<id>urn:sha1:8fe44c080a53ac0ccbe88053a2e40f9acca33091</id>
<content type='text'>
No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN3.1 DML calculation support</title>
<updated>2021-06-04T20:39:18Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-05-19T16:22:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=74458c081fcfb0423877e630de2746daefdb16e4'/>
<id>urn:sha1:74458c081fcfb0423877e630de2746daefdb16e4</id>
<content type='text'>
DML (Display mode library) is used for calculating watermarks, bandwidth
and for validating display configurations.

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: fix odm scaling</title>
<updated>2021-05-27T16:26:17Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2021-05-10T14:19:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=6566cae7aef30da8833f1fa0eb854baf33b96676'/>
<id>urn:sha1:6566cae7aef30da8833f1fa0eb854baf33b96676</id>
<content type='text'>
There are two issues with scaling calculations, odm recout
calculation and matching viewport to actual recout.

This change fixes both issues. Odm recout calculation via
special casing and viewport matching issue by reworking
the viewport calcualtion to use scaling ratios and recout
to derrive the required offset and size.

Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Cleanup DML DSC input bpc validation</title>
<updated>2021-04-09T20:53:32Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-03-26T18:25:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=091e3131a8c237e17e310db2b3b59aa576075574'/>
<id>urn:sha1:091e3131a8c237e17e310db2b3b59aa576075574</id>
<content type='text'>
[Why &amp; How]
Pipe input DSC bpc has a type mismatch with maximum DSC
input bpc - align the maximum with the pipe input type,
unsigned integer.

When checking the type we shoudl also check for an
implicit value of 0 and align with what the spreadsheet
does - default to max.

Rename output_bpc to dsc_input_bpc to reflect what the
field is actually used for.

Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Reviewed-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: DIO Supported for virtual displays</title>
<updated>2021-02-09T20:48:18Z</updated>
<author>
<name>Wesley Chalmers</name>
<email>Wesley.Chalmers@amd.com</email>
</author>
<published>2021-01-29T17:37:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=91a51fbf24e2d9e996987c7fadf666152a9f536a'/>
<id>urn:sha1:91a51fbf24e2d9e996987c7fadf666152a9f536a</id>
<content type='text'>
[WHY]
Virtual displays do not use the backend of the pipe, and so have
infinite backend bandwidth.

[HOW]
Add a skip_dio_check bool to the VBA struct, which is used to override
the DIOSupport calculations.

Signed-off-by: Wesley Chalmers &lt;Wesley.Chalmers@amd.com&gt;
Reviewed-by: Jun Lei &lt;Jun.Lei@amd.com&gt;
Acked-by: Anson Jacob &lt;Anson.Jacob@amd.com&gt;
Acked-by: Chris Park &lt;Chris.Park@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: remove unused dml variables</title>
<updated>2020-11-16T17:18:55Z</updated>
<author>
<name>Dmytro Laktyushkin</name>
<email>Dmytro.Laktyushkin@amd.com</email>
</author>
<published>2020-08-27T19:23:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=89c5ca3b5e50acdb0ed69d8af2cf5a9b7e253dae'/>
<id>urn:sha1:89c5ca3b5e50acdb0ed69d8af2cf5a9b7e253dae</id>
<content type='text'>
Signed-off-by: Dmytro Laktyushkin &lt;Dmytro.Laktyushkin@amd.com&gt;
Acked-by: Bindu Ramamurthy &lt;bindu.r@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
