linux-dev/drivers/gpu/drm/amd/display/dc/dsc, branch master

drm/amd: Fix spelling typo in comments

2022-06-03T20:43:36Z

Fix spelling typo in comments. Reported-by: k2ci Signed-off-by: pengfuyuan Signed-off-by: Alex Deucher

drm/display: Move DSC header and helpers into display-helper module

2022-04-25T09:19:36Z

DSC is the Display Stream Compression standard for DisplayPort. Move the DSC code into display/ and split the header into files for protocol core and DRM helpers. Adapt all users of the code. No functional changes. To avoid the proliferation of Kconfig options, DSC is part of DRM's support for DisplayPort. If necessary, a new option could make DSC an independent feature. Signed-off-by: Thomas Zimmermann Reviewed-by: Javier Martinez Canillas Link: https://patchwork.freedesktop.org/patch/msgid/20220421073108.19226-6-tzimmermann@suse.de

drm: Rename dp/ to display/

2022-04-25T09:17:45Z

Rename dp/ to display/ to account for additional display-related helpers, such as HDMI. Update all related include statements. No functional changes. Various drivers, such as i915 and amdgpu, use similar naming scheme by putting code for video-output standards into a local display/ directory. The new directory's name is aligned with this convention. v2: * update commit message (Javier) Signed-off-by: Thomas Zimmermann Reviewed-by: Lyude Paul Reviewed-by: Javier Martinez Canillas Reviewed-by: Alex Deucher Link: https://patchwork.freedesktop.org/patch/msgid/20220421073108.19226-3-tzimmermann@suse.de

drm/amd/display: Correct Slice reset calculation

2022-04-06T15:26:19Z

[Why] Once DSC slice cannot fit pixel clock, we incorrectly reset min slices to 0 and allow max slice to operate, even when max slice itself cannot fit the pixel clock properly. [How] Change the sequence such that we correctly determine DSC is not possible when both min slices and max slices cannot fit pixel clock per slice. Reviewed-by: Wenjing Liu Acked-by: Alex Hung Signed-off-by: Chris Park Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/dp: Move public DisplayPort headers into dp/

2022-01-17T10:25:44Z

Move all public DisplayPort headers into dp/ and update users. No functional changes. v3: * rebased onto latest drm-tip Signed-off-by: Thomas Zimmermann Acked-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20220114114535.29157-5-tzimmermann@suse.de

drm/amd/display: fixed an error related to 4:2:0/4:2:2 DSC

2021-11-24T19:06:52Z

[Why] OPTC_BYTES_PER_PIXEL calculation for 4:2:2 and 4:2:0 could have error. [How] Change to use following formula: OPTC_DSC_BYTES_PER_PIXEL = ceiling((chunk size * 2^28) / slice width) v2: squash in 64 bit divide fix (Alex) Reviewed-by: Wenjing Liu Acked-by: Qingqing Zhuo Signed-off-by: Bing Guo Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Enable DSC over eDP

2021-11-22T19:45:01Z

[why] - Adding a DM interface to enable DSC over eDP on Linux - DSC over eDP will allow to power savings by reducing the bandwidth required to support panel's modes - Apply link optimization algorithm to reduce link bandwidth when DSC is enabled [how] - Read eDP panel's DSC capabilities - Apply DSC policy on eDP panel based on its DSC capabilities - Enable DSC encoder's on the pipe - Enable DSC on panel's side by setting DSC_ENABLE DPCD register - Adding link optimization algorithm to reduce link rate or lane count based Reviewed-by: Nicholas Kazlauskas Acked-by: Wayne Lin Signed-off-by: Mikita Lipski Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Fix Coverity Issues

2021-11-17T21:58:08Z

[Why] Coverity discovers holes in logic that needs to be addressed for improved code integrity. [How] Address issues found by coverity without changing the actual logic. Reviewed-by: Aric Cyr Acked-by: Anson Jacob Tested-by: Daniel Wheeler Signed-off-by: Chris Park Signed-off-by: Alex Deucher

drm/amd/display: move FPU associated DSC code to DML folder

2021-10-28T18:26:14Z

[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DSC to DML, where all FPU code should locate. This change does not refactor any functions but move code around. Cc: Christian König Cc: Hersen Wu Cc: Anson Jacob Cc: Harry Wentland Reviewed-by: Rodrigo Siqueira Acked-by: Agustin Gutierrez Tested-by: Anson Jacob Tested-by: Daniel Wheeler Signed-off-by: Qingqing Zhuo Acked-by: Christian König Signed-off-by: Alex Deucher

drm/amd/display: move bpp range decision in decide dsc bw range function

2021-09-14T19:57:09Z

[why] Before get dsc bw range is used to compute DSC bw range based on the given fixed bpp min/max input. The new change will merge any specs, signal, timing specific bpp range decision into this function. So the function needs to make a decision with all aspects considered. Acked-by: Mikita Lipski Signed-off-by: Wenjing Liu Reviewed-by: George Shen Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher