linux-dev/drivers/gpu/drm/amd/display/dc/inc/hw, branch linus/master

drm/amd/display: Wait DMCUB to idle state before reset.

2022-06-01T19:56:48Z

[WHY] Very low rate to cause memory access issue while resetting DMCUB after the halt command was sent to it. The process of stopping fw of DMCUB may be timeout, that means it is not in idle state, such as the window frames may still be kept in cache, so reset by force will cause MMHUB hang. [HOW] After the halt command was sent, keep checking the DMCUB state until it is idle. Reviewed-by: Eric Yang Reviewed-by: Nicholas Kazlauskas Acked-by: Jasdeep Dhillon Tested-by: Daniel Wheeler Signed-off-by: hengzhou Signed-off-by: Alex Deucher

drm/amd/display: Pass the new context into disable OTG WA

2022-06-01T19:56:48Z

[Why] When enabling an HPO stream for the first time after having previously enabled a DIO stream there may be lingering DIO FIFO errors even though the DIO is no longer enabled. These can cause display clock change to hang if we don't apply the OTG disable workaround since the ramping logic is tied to OTG on. [How] The workaround wasn't being applied in the sequence of: 1 DIO stream 0 streams 1 HPO stream because current_state has no stream or planes in its context - and it's only swapped after optimize has finished. We should be using the incoming context instead to determine whether this logic is needed or not. Reviewed-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Jasdeep Dhillon Tested-by: Daniel Wheeler Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher

drm/amd/display: revert Blank eDP on disable/enable drv

2022-06-01T19:56:48Z

why and how: Revert this change. It was causing a black screen with certain blocks Reviewed-by: George Shen Acked-by: Jasdeep Dhillon Tested-by: Daniel Wheeler Signed-off-by: Leung, Martin Signed-off-by: Alex Deucher

drm/amd/display: Add new DSC interface to disconnect from pipe

2022-05-04T14:43:55Z

[Why & How] Add new DSC interface to disconnect from pipe. Reviewed-by: Alvin Lee Acked-by: Wayne Lin Signed-off-by: Eric Bernstein Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: update dcn315 clk table read

2022-04-25T21:06:16Z

Clean up the sequence by making sure clk_mgr always builds a reasonable clock table regardless of what we read from smu by moving all defaults from resource soc struct to clk_mgr. Now the only thing resource soc update does is read the clock table and apply any DC specific policy decisions to how clocks are populated in dml soc. Reviewed-by: Qingqing Zhuo Acked-by: Tom Chung Signed-off-by: Dmytro Laktyushkin Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add odm seamless boot support

2022-04-12T18:18:37Z

[WHY] Implement changes to transition from Pre-OS odm to Post-OS odm support. Seamless boot case is also considered. [HOW] Revised validation logic when marking for seamless boot. Init resources accordingly when Pre-OS has odm enabled. Reset odm and det size when transitioning Pre-OS odm to Post-OS non-odm to avoid corruption. Apply logic to set odm accordingly upon commit. Reviewed-by: Nicholas Kazlauskas Acked-by: Pavle Kotarac Signed-off-by: Duncan Ma Signed-off-by: Alex Deucher

drm/amd/display: Add support for zstate during extended vblank

2022-03-25T16:40:25Z

[why] When we enter FREESYNC_STATE_VIDEO, we want to use the extra vblank portion to enter zstate if possible. [how] When we enter freesync, a full update is triggered and the new vtotal with extra lines is passed to dml in a stream update. The time gained from extra vblank lines is calculated in microseconds. We allow zstate entry if the time gained is greater than 5 ms, which is the current policy. Furthermore, an optimized value for min_dst_y_next_start is calculated and written to its register. When exiting freesync, another full update is triggered and default values are restored. Reviewed-by: Nicholas Kazlauskas Acked-by: Alex Hung Signed-off-by: Gabe Teeger Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add save/restore PANEL_PWRSEQ_REF_DIV2

2022-03-15T18:42:01Z

[why] DCN31 has this in zstate save/restore sequence. need for non_zstate supported ASIC [how] add this PANEL_PWRSEQ_REF_DIV2 to existing panel_cntl_hw_init structure. Reviewed-by: Nicholas Kazlauskas Acked-by: Agustin Gutierrez Signed-off-by: Charlene Liu Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Wait for hubp read line for Pollock

2022-03-15T18:41:55Z

[Why] Underflow occurred while hubp ret pipe read is idle and the second pipe is powered up and added. Flickering and underflow are only observed on Pollock. [How] Check the hubp ret pipe read prior to unlock pipes. Reviewed-by: Hersen Wu Reviewed-by: Aric Cyr Acked-by: Agustin Gutierrez Signed-off-by: Becle Lee Tested-by: Daniel Wheeler Signed-off-by: Alex Deucher

drm/amd/display: Add pstate verification and recovery for DCN31

2022-03-15T18:33:57Z

[Why] To debug when p-state is being blocked and avoid PMFW hangs when it does occur. [How] Re-use the DCN10 hardware sequencer by adding a new interface for verifying p-state high on the hubbub. The interface is mostly the same as the DCN10 interface, but the bit definitions have changed for the debug bus. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Eric Yang Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher