<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/display/dc/irq/Makefile, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/irq/Makefile?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/display/dc/irq/Makefile?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-05-10T21:53:13Z</updated>
<entry>
<title>drm/amd/display: remove redundant CONFIG_DRM_AMD_DC_DCN in irq</title>
<updated>2022-05-10T21:53:13Z</updated>
<author>
<name>Alex Hung</name>
<email>alex.hung@amd.com</email>
</author>
<published>2022-04-25T19:49:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=47f7d80715704a6c4f071ab2fa38dd2e3ae4a184'/>
<id>urn:sha1:47f7d80715704a6c4f071ab2fa38dd2e3ae4a184</id>
<content type='text'>
[Why &amp; How]
CONFIG_DRM_AMD_DC_DCN is used by pass the compilation failures, but DC
code should be OS-agnostic.

This patch fixes it by removing unnecessasry CONFIG_DRM_AMD_DC_DCN
in irq directory.

Reviewed-by: Rodrigo Siqueira &lt;Rodrigo.Siqueira@amd.com&gt;
Acked-by: Stylon Wang &lt;stylon.wang@amd.com&gt;
Signed-off-by: Alex Hung &lt;alex.hung@amd.com&gt;
Tested-by: Daniel Wheeler &lt;daniel.wheeler@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN315 IRQ</title>
<updated>2022-02-18T19:07:00Z</updated>
<author>
<name>Qingqing Zhuo</name>
<email>qingqing.zhuo@amd.com</email>
</author>
<published>2022-02-03T23:07:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=92d0c2ebe564f492ea71bf2ca81de5d95d58d6de'/>
<id>urn:sha1:92d0c2ebe564f492ea71bf2ca81de5d95d58d6de</id>
<content type='text'>
Add irq interfaces for DCN 3.1.5.

Signed-off-by: Qingqing Zhuo &lt;qingqing.zhuo@amd.com&gt;
Acked-by: Harry Wentland &lt;Harry.Wentland@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN</title>
<updated>2021-10-04T19:23:02Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-10-01T14:29:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=519607a2f7798decb9c891a4f706aaf780f5a677'/>
<id>urn:sha1:519607a2f7798decb9c891a4f706aaf780f5a677</id>
<content type='text'>
No need for a separate kconfig option at this point.

Reviewed-by: Zhan Liu &lt;zhan.liu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: add cyan_skillfish display support</title>
<updated>2021-10-04T19:22:57Z</updated>
<author>
<name>Zhan Liu</name>
<email>zhan.liu@amd.com</email>
</author>
<published>2021-09-25T07:01:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3f68c01be9a2227de1e190317fe34a6fb835a094'/>
<id>urn:sha1:3f68c01be9a2227de1e190317fe34a6fb835a094</id>
<content type='text'>
[Why]
add display related cyan_skillfish files in.

makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.

v2: squash in clang fixes from Harry, Nathan
v3: squash in missing CONFIG_DRM_AMD_DC check (Alex)

Signed-off-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Signed-off-by: Zhan Liu &lt;zhan.liu@amd.com&gt;
Reviewed-by: Charlene Liu &lt;charlene.liu@amd.com&gt;
Acked-by: Jun Lei &lt;jun.lei@amd.com&gt;
Acked-by: Harry Wentland &lt;harry.wentland@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN</title>
<updated>2021-06-22T20:51:45Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2021-06-21T20:51:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8fe44c080a53ac0ccbe88053a2e40f9acca33091'/>
<id>urn:sha1:8fe44c080a53ac0ccbe88053a2e40f9acca33091</id>
<content type='text'>
No need for a separate flag now that DCN3.1 is not in bring up.
Fold into DRM_AMD_DC_DCN like previous DCN IPs.

Reviewed-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add DCN3.1 IRQ manager</title>
<updated>2021-06-04T20:39:18Z</updated>
<author>
<name>Nicholas Kazlauskas</name>
<email>nicholas.kazlauskas@amd.com</email>
</author>
<published>2021-05-19T16:27:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ef22ccbcfbc9f474d3448f2d5e53dc6a51f2f62d'/>
<id>urn:sha1:ef22ccbcfbc9f474d3448f2d5e53dc6a51f2f62d</id>
<content type='text'>
Add IRQ services for DCN3.1 to handle hardware generated interrupts.

Acked-by: Huang Rui &lt;ray.huang@amd.com&gt;
Signed-off-by: Nicholas Kazlauskas &lt;nicholas.kazlauskas@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Initial DC support for Beige Goby</title>
<updated>2021-05-20T02:42:00Z</updated>
<author>
<name>Aurabindo Pillai</name>
<email>aurabindo.pillai@amd.com</email>
</author>
<published>2021-03-15T18:55:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cd6d421e3d1ad5926b74091254e345db730e7706'/>
<id>urn:sha1:cd6d421e3d1ad5926b74091254e345db730e7706</id>
<content type='text'>
[Why&amp;How]
Add Beige Goby (DCN303) resource, irq service, &amp; dmub loader.

v2: fix nbio include (Alex)

Signed-off-by: Chris Park &lt;Chris.Park@amd.com&gt;
Signed-off-by: Aurabindo Pillai &lt;aurabindo.pillai@amd.com&gt;
Acked-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)</title>
<updated>2020-11-04T22:11:37Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-11-02T20:37:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=20f2ffe504728612d7b0c34e4f8280e34251e704'/>
<id>urn:sha1:20f2ffe504728612d7b0c34e4f8280e34251e704</id>
<content type='text'>
Avoids confusion in configurations.

v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled
v3: rebase on latest code

Reviewed-by: Luben Tuikov &lt;luben.tuikov@amd.com&gt; (v1)
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: Add support for DCN302 (v2)</title>
<updated>2020-10-12T18:02:51Z</updated>
<author>
<name>Bhawanpreet Lakha</name>
<email>Bhawanpreet.Lakha@amd.com</email>
</author>
<published>2020-09-29T18:52:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=36d26912e8d854853e3cdb300664db274a6636cf'/>
<id>urn:sha1:36d26912e8d854853e3cdb300664db274a6636cf</id>
<content type='text'>
 - add DCN302 resource, irq service, dmub loader,
 - handle  DC_VERSION_DCN_3_02
 - define DCN302 power gating functions
 - handle DCN302 in GPIO files
 - define I2C regs
 - add CONFIG_DRM_AMD_DC_DCN3_02 guard

v2: rebase fixes (Alex)

Signed-off-by: Joshua Aberback &lt;joshua.aberback@amd.com&gt;
Signed-off-by: Bhawanpreet Lakha &lt;Bhawanpreet.Lakha@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/display: dc/irq: add support for DCE6 (v4)</title>
<updated>2020-07-27T20:46:02Z</updated>
<author>
<name>Mauro Rossi</name>
<email>issor.oruam@gmail.com</email>
</author>
<published>2020-02-08T09:41:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=61bf32937bdd05fdf74292460d56936d63beaba5'/>
<id>urn:sha1:61bf32937bdd05fdf74292460d56936d63beaba5</id>
<content type='text'>
[Why]
irq service requires changes for DCE6 support

[How]
(v1) DCE6 targets are added replicating existing DCE8 implementation.
     due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks,
     dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h

(v2) DCE6 headers used adding the necessary vblank irq registers
     (INT_MASK and VBLANK_STATUS) and vblank irq masks as implemented
     in amdgpu driver.
     Add vblank_irq_info_funcs_dce60 with .set and .ack as per commit
     b10d51f ("drm/amd/display: Add interrupt entries for VBLANK isr.")
     and use it in vblank_int_entry(reg_num) macro definition

(v3) updated due to following kernel 5.3 commit:
     4fc4dca ("drm/amd: drop use of drmp.h in os_types.h")

(v4) updated due to following kernel 5.6 commit:
     d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs")

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Mauro Rossi &lt;issor.oruam@gmail.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
