linux-dev/drivers/gpu/drm/amd/include/asic_reg/dcn, branch linus/masterLinux kernel development work - see feature brancheshttps://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/dcn?h=linus%2Fmaster2022-05-26T18:56:32Zdrm/amd/display: Add HDMI_ACP_SEND register2022-05-26T18:56:32ZAlan LiuHaoPing.Liu@amd.com2022-05-17T14:30:00Zurn:sha1:6880ed280edf292c542aa87567547ffb9c222597
Define HDMI_ACP_SEND register shift/mask.
Signed-off-by: Alan Liu <HaoPing.Liu@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: add DCN 3.1.5 registers2022-02-18T19:07:00ZQingqing Zhuoqingqing.zhuo@amd.com2022-01-27T02:52:11Zurn:sha1:5b723b12301272ed3c6c99c4ad8b43a520f880ea
Add DCN 3.1.5 and DPCS 4.2.2 register headers.
Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Change-Id: I5588a1c422ae384cc76aa42380545dfc1aad1948
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Add register headers for DCN 3.1.62022-02-17T20:44:45ZLeo Lisunpeng.li@amd.com2022-01-27T17:06:53Zurn:sha1:64b14a184e83eb62ea0615e31a409956049d40e7
Add register headers for the following IPs:
- DCN 3.1.6
- DPCS 4.2.3
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: move dpcs_3_0_3 headers from dcn to dpcs2022-02-07T23:03:50ZAlex Deucheralexander.deucher@amd.com2022-02-03T18:04:46Zurn:sha1:4a5dc6c73dbec54648fe01af2f1818dc3ae90d5d
To align with other headers.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: move dpcs_3_0_0 headers from dcn to dpcs2022-02-07T23:03:50ZAlex Deucheralexander.deucher@amd.com2022-02-03T17:52:21Zurn:sha1:68550cbc6129159b7a6434796b721e8b66ee12f6
To align with other headers.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add missing license to dpcs_3_0_0 headers2022-02-07T23:03:50ZAlex Deucheralexander.deucher@amd.com2022-01-28T21:26:08Zurn:sha1:120cc6e67a5e34069693cf1711ea222b8c414685
MIT.
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Disable hdmistream and hdmichar clocks2021-10-19T21:20:28ZJake Wanghaonan.wang2@amd.com2021-09-23T03:37:52Zurn:sha1:e7414a1a185ead49e8b7e0fa6952e74cfe4a76f4
[Why & How]
Disable hdmistream and hdmichar root clocks when not being used.
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Agustin Gutierrez Sanchez <agustin.gutierrez@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add cyan_skillfish asic header files2021-09-29T21:30:00ZZhan Liuzhan.liu@amd.com2021-09-25T07:51:08Zurn:sha1:0ad53fe3ae82443c74ff8cfd7bd13377cc1134a3
This patch is to add cyan_skillfish asic header files.
Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Acked-by: Jun Lei <jun.lei@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: DMUB Outbound Interrupt Process-X862021-07-08T19:14:36ZChun-Liang ChangChun-Liang.Chang@amd.com2021-06-11T03:05:20Zurn:sha1:556a979d3c50960acd96efded7801970bd989236
[Why]
dmub would notify x86 response time violation by GPINT_DATAOUT
[How]
1. Use GPINT_DATAOUT to trigger x86 interrupt
2. Register GPINT_DATAOUT interrupt handler.
3. Trigger ACR while GPINT_DATAOUT occurred.
Signed-off-by: Chun-Liang Chang <Chun-Liang.Chang@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Add interface to get Calibrated Avg Level from FIFO2021-06-15T21:25:41ZWesley ChalmersWesley.Chalmers@amd.com2021-05-06T17:22:19Zurn:sha1:a659f2fdf8b9b186c9324e05baa9e2835d47c7d2
[WHY]
Hardware has handed down a new sequence requiring the value of this
register be read from clk_mgr.
Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Anson Jacob <Anson.Jacob@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>