<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/include/asic_reg/gc, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/gc?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/gc?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-04-28T21:48:28Z</updated>
<entry>
<title>drm/amdgpu: add gc v11_0_0 ip headers v11</title>
<updated>2022-04-28T21:48:28Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2021-12-30T08:56:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f33ac92f9c010be84ecbbec7e30990012be806e8'/>
<id>urn:sha1:f33ac92f9c010be84ecbbec7e30990012be806e8</id>
<content type='text'>
Add gc v11_0_0 register offset and shift masks
header files (Hawking)

Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Reviewed-by: Likun Gao &lt;Likun.Gao@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: add regCP_MEx_INT_STAT_DEBUG for Aldebaran debugging</title>
<updated>2021-08-06T01:17:59Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2021-03-23T16:22:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d2a266fad506aa3dc143280dcf2dd732b40bcdd3'/>
<id>urn:sha1:d2a266fad506aa3dc143280dcf2dd732b40bcdd3</id>
<content type='text'>
Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: only harvest gcea/mmea error status in arcturus</title>
<updated>2021-04-21T01:35:45Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2021-04-16T09:34:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=53ee6609b42e09f89bf2cdd15a340c236694ecd3'/>
<id>urn:sha1:53ee6609b42e09f89bf2cdd15a340c236694ecd3</id>
<content type='text'>
SDP RdRspStatus/WrRspStatus or first parity error on
RdRsp data can cause system fatal error in arcturus.
GPU will be freezed in such case.

Driver needs to harvest these error information before
reset the GPU. Check error type to avoid harvest normal
gcea/mmea information.

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Reviewed-by: Stanley Yang &lt;Stanley.Yang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headers</title>
<updated>2021-04-09T20:46:59Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2021-03-26T11:07:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=53df89ddc0ccb016edbf8c4cc1d66e75ade28837'/>
<id>urn:sha1:53df89ddc0ccb016edbf8c4cc1d66e75ade28837</id>
<content type='text'>
Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add gc v9_4_2 ip headers (v3)</title>
<updated>2021-03-10T05:00:48Z</updated>
<author>
<name>Hawking Zhang</name>
<email>Hawking.Zhang@amd.com</email>
</author>
<published>2020-12-07T12:14:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=301a16138285ebfce961dbaa7d9da86c26ca7428'/>
<id>urn:sha1:301a16138285ebfce961dbaa7d9da86c26ca7428</id>
<content type='text'>
v1: Add gc v9_4_2 register offset and shift
masks in header files (Hawking)
v2: Clean up gc v9_4_2 registers (Alex)
v3: update registers (Alex)

Signed-off-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Reviewed-by: Kevin Wang &lt;kevin1.wang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add GC 10.3 NOALLOC registers</title>
<updated>2020-10-23T19:33:47Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-05-01T20:41:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d02792041c17c9f8e1f9ac1420dcfb7fe13b256c'/>
<id>urn:sha1:d02792041c17c9f8e1f9ac1420dcfb7fe13b256c</id>
<content type='text'>
This adds the NOALLOC registers.

Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add missing newline at eof</title>
<updated>2020-10-15T16:20:12Z</updated>
<author>
<name>Tom Rix</name>
<email>trix@redhat.com</email>
</author>
<published>2020-10-14T21:18:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=234de272b76fedaf71ffe40f8e80212c8d32cc23'/>
<id>urn:sha1:234de272b76fedaf71ffe40f8e80212c8d32cc23</id>
<content type='text'>
Representative checkpatch.pl warning

WARNING: adding a line without newline at end of file
 30: FILE: drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h:30:
+#endif

Signed-off-by: Tom Rix &lt;trix@redhat.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: update athub interrupt harvesting handle</title>
<updated>2020-09-22T21:37:38Z</updated>
<author>
<name>Stanley.Yang</name>
<email>Stanley.Yang@amd.com</email>
</author>
<published>2020-09-15T08:15:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3f975d0f71d384825f47c3598d1d5358e40a57f5'/>
<id>urn:sha1:3f975d0f71d384825f47c3598d1d5358e40a57f5</id>
<content type='text'>
GCEA/MMHUB EA error should not result to DF freeze, this is
fixed in next generation, but for some reasons the GCEA/MMHUB
EA error will result to DF freeze in previous generation,
diver should avoid to indicate GCEA/MMHUB EA error as hw fatal
error in kernel message by read GCEA/MMHUB err status registers.

Changed from V1:
    make query_ras_error_status function more general
    make read mmhub er status register more friendly

Changed from V2:
    move ras error status query function into do_recovery workqueue

Changed from V3:
    remove useless code from V2, print GCEA error status
    instance number

Signed-off-by: Stanley.Yang &lt;Stanley.Yang@amd.com&gt;
Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add the GC 10.3 VRS registers</title>
<updated>2020-09-17T22:00:50Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2020-05-01T20:42:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7663edc13ed0a5390944e49038815ee0a8e7ae05'/>
<id>urn:sha1:7663edc13ed0a5390944e49038815ee0a8e7ae05</id>
<content type='text'>
Add the VRS registers.

Reviewed-by: Hawking Zhang &lt;Hawking.Zhang@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Add RLC_CGTT_MGCG_OVERRIDE to gfx 10.3 headers</title>
<updated>2020-07-27T20:20:40Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2020-07-23T12:51:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=26cfd12b5e24993ac943ac37044128fe33b3ed94'/>
<id>urn:sha1:26cfd12b5e24993ac943ac37044128fe33b3ed94</id>
<content type='text'>
Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
