linux-dev/drivers/gpu/drm/amd/include/asic_reg/gca, branch masterLinux kernel development work - see feature brancheshttps://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/gca?h=master2016-11-11T15:21:08Zdrm/amd/amdgpu: add SI defines/registers2016-11-11T15:21:08ZTom St Denistom.stdenis@amd.com2016-11-07T19:06:01Zurn:sha1:5e2e2119955a9f18beccd6603bdd255dad18eb15
Add missing gca MMIO registers and defines necessary for the
next patch which re-works a lot of gfx v6 to use the new SI
headers.
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Introduction of SI registers (v2)2016-11-11T15:21:07ZTom St Denistom.stdenis@amd.com2016-10-26T15:58:25Zurn:sha1:de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33
This introduces the SI registers in the amdgpu
driver style.
v2: squash duplicates fix
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/powerplay: add shared definitions for di/dt feature.2016-07-07T19:06:22ZRex ZhuRex.Zhu@amd.com2016-06-08T04:52:16Zurn:sha1:9a88d22bb090f39e234bec9e4d416c8acdcdbb93
v1: delete some comflict definitions between polaris and fiji.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: remove gfx8 registers that vary between asics2016-07-07T19:06:21ZKen WangQingqing.Wang@amd.com2016-07-01T05:54:23Zurn:sha1:a334bc7df010b5d427b6f37bc9db34759e372a2e
those register mask definitions are different in polaris compare to
former gfx 8 gpus, so remove them from misusing.
Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx80: Add QUICK_PG bit to GFX header and use it.2016-07-07T18:51:19ZTom St Denistom.stdenis@amd.com2016-06-03T18:31:46Zurn:sha1:78f73bf03c131c5428383aa34e273be80965dd06
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmRLC_CGCG_CGLS_CTRL_3D & mmRLC_CGCG_RAMP_CTRL_3D2016-05-05T00:25:02ZFlora CuiFlora.Cui@amd.com2015-11-05T04:42:59Zurn:sha1:d7120b8f227bd0aaa87f10861848faff47eed7af
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/gfx7: add MTYPE definition2016-03-17T17:15:43ZFlora Cuiflora.cui@amd.com2015-10-12T02:12:03Zurn:sha1:b9c743b85dc378510ef0e5ebe3c2e4ac1495c410
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: add new gfx8 register definitions for EDC2015-12-02T20:54:18ZAlex Deucheralexander.deucher@amd.com2015-11-24T22:42:02Zurn:sha1:aa5e24e5f8a83b19b1b19964f35562c7a42636e2
EDC is a RAS feature for on chip memory.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add GFX 8.1 register headers2015-10-28T20:49:03ZAlex Deucheralexander.deucher@amd.com2015-10-23T22:53:36Zurn:sha1:6bd53c4125e545a495fba63024d5522e33c600f5
Minor differences compared to GFX 8.0
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add GCA 8.0 register headers2015-06-04T01:02:56ZAlex Deucheralexander.deucher@amd.com2015-04-16T19:21:21Zurn:sha1:675892a184ee337471077e762a26f878f21535ae
These are register headers for the GCA (Graphics and Compute Array)
block on the GPU.
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Jammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>