linux-dev/drivers/gpu/drm/amd/include/asic_reg/mmhub, branch linus/masterLinux kernel development work - see feature brancheshttps://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/mmhub?h=linus%2Fmaster2022-05-05T20:51:45Zdrm/amdgpu: add mmhub v3_0_2 ip headers2022-05-05T20:51:45ZHawking ZhangHawking.Zhang@amd.com2022-02-06T16:34:00Zurn:sha1:fd1e77d915bcbd65a5ee667b94b73628f77c818e
Add mmhub v3_0_2 register offset and shift masks
v2: update to latest headers
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub v3_0_0 ip headers v62022-05-04T13:57:16ZHawking ZhangHawking.Zhang@amd.com2021-11-18T05:42:36Zurn:sha1:9f99d9830554a13dc9f5e47dbaddfae36cbf416e
Add mmhub v3_0_0 register offset and shift masks
header files (Hawking)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub v1_7 ip headers (v3)2021-03-10T05:01:00ZHawking ZhangHawking.Zhang@amd.com2020-12-07T12:17:45Zurn:sha1:b9dd2add842c0e4d50cbafe135356c2431fdbc8b
v1: Add mmhub v1_7 register offset and
shift masks in header files (Hawking)
v2: Clean up mmhub v1_7 registers (Alex)
v3: Update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add vangogh asic header files (v2)2020-10-05T19:14:02ZHuang Ruiray.huang@amd.com2019-10-20T00:39:44Zurn:sha1:a5b2c10c05ef12739be9907cc35acd33dff09020
This patch is to add vangogh asic header files.
v2: squash in updates
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update mmhub 9.4.1 header files for Acrturus2020-01-22T21:35:42ZDennis LiDennis.Li@amd.com2020-01-13T08:15:38Zurn:sha1:f519cd13c23e8c884011295b205c1463babbf416
Add mask & shift definition of MAM_D(0~3)MEM for all mmhub
ranges.
Signed-off-by: Dennis Li <Dennis.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: refine query function of mmhub EDC counter in vg202019-11-22T19:26:46ZDennis LiDennis.Li@amd.com2019-11-19T08:02:28Zurn:sha1:8781e5df119fbce754bf027c691208f677dc07c8
Add codes to print the detail EDC info for the subblock of mmhub
v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header
files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local
static variable and function.
v3: squash in DC fix
Signed-off-by: Dennis Li <dennis.li@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: implement querying ras error count for mmhub2019-08-15T15:51:50ZTao Zhoutao.zhou1@amd.com2019-08-13T07:46:03Zurn:sha1:d6e0cbb152b35833a26772c86b338d8297ce609d
get mmhub ea ras error count by accessing EDC_CNT register
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Guchun Chen <guchun.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add mmhub 9.4.1 header files for Acrturus2019-07-18T19:18:01ZLe Male.ma@amd.com2018-08-29T08:49:19Zurn:sha1:0e96cf7f676972b1154c4c2b68e878266a405a84
mmhub is the GPU memory hub used by SDMA and VCN.
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add MMHUB 2.0 register headers2019-06-20T20:54:39ZHawking ZhangHawking.Zhang@amd.com2019-03-03T03:29:18Zurn:sha1:f519f0be45da3bd09efbcaf9930dac34949f9f82
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/include: Add mmhub 9.4 reg offsets and shift-mask2018-12-05T22:49:50ZLeo Lisunpeng.li@amd.com2018-11-22T14:39:17Zurn:sha1:d4295e12796e747f9a624a56cd54de51fb2b3bdd
In particular, we need the mmMC_VM_XGMI_LFB_CNTL register, for
determining if xGMI is enabled on VG20. This will be used by DC to
determine the correct spread spectrum adjustment for display and audio
clocks.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>