linux-dev/drivers/gpu/drm/amd/include/asic_reg/nbio, branch masterLinux kernel development work - see feature brancheshttps://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/nbio?h=master2022-08-25T17:52:48Zdrm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.02022-08-25T17:52:48ZTim Huangtim.huang@amd.com2022-08-15T05:03:49Zurn:sha1:ad3b0b99113783f697579c7b09285916019865ea
Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro
definitions for AMD_CG_SUPPORT_BIF_LS.
Signed-off-by: Tim Huang <tim.huang@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: enable ASPM support for PCIE 7.4.0/7.6.02022-06-08T15:43:00ZEvan Quanevan.quan@amd.com2022-04-28T08:51:04Zurn:sha1:62f8f5c3bfc2968461b0a74f0e393325bec16c69
Enable ASPM support for PCIE 7.4.0 and 7.6.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add CSDMA reg offsets for NBIO v7.7.02022-06-03T20:44:15ZXiaojian DuXiaojian.Du@amd.com2022-05-20T14:27:57Zurn:sha1:cb12d72b426caa7594890c62df69fe4b83c96e58
This patch will add CSDMA reg offsets for NBIO v7.7.0
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add nbio v7_7_0 ip headers2022-05-06T14:36:13ZHuang Ruiray.huang@amd.com2021-08-02T00:40:47Zurn:sha1:4debe753953f20325b1d8a5e0958c0d38c9fd32f
Add nbio v7.7.0 offset and shift mask ip header files.
v2: squash in updates (Alex)
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add nbio v4_3_0 ip headers v62022-05-04T13:52:41ZHawking ZhangHawking.Zhang@amd.com2021-12-30T11:18:08Zurn:sha1:e19920c6a08334d9a38b5edb4b03b62d989e6ae1
Add nbio v4_3_0 register offset and shift masks
header files (Hawking)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: clean up some leftovers from bring up2021-12-16T19:08:20ZAlex Deucheralexander.deucher@amd.com2021-12-13T19:42:43Zurn:sha1:109a357f287c3b14a43216104299aafc1fa23cbc
Some old registers leftover from pre-silicon. No longer
relevant on real hardware. Remove.
Reviewed-by: James Zhu <James.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add vangogh asic header files (v2)2020-10-05T19:14:02ZHuang Ruiray.huang@amd.com2019-10-20T00:39:44Zurn:sha1:a5b2c10c05ef12739be9907cc35acd33dff09020
This patch is to add vangogh asic header files.
v2: squash in updates
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: cleanup all virtualization detection routine2020-04-01T18:44:42ZMonk LiuMonk.Liu@amd.com2020-03-04T06:02:55Zurn:sha1:3aa0115d238c71423d0e212138678a8cf51d4361
we need to move virt detection much earlier because:
1) HW team confirms us that RCC_IOV_FUNC_IDENTIFIER will always
be at DE5 (dw) mmio offset from vega10, this way there is no
need to implement detect_hw_virt() routine in each nbio/chip file.
for VI SRIOV chip (tonga & fiji), the BIF_IOV_FUNC_IDENTIFIER is at
0x1503
2) we need to acknowledged we are SRIOV VF before we do IP discovery because
the IP discovery content will be updated by host everytime after it recieved
a new coming "REQ_GPU_INIT_DATA" request from guest (there will be patches
for this new handshake soon).
Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Reviewed-by: Emily Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add pcie bif ras related registers2019-09-16T15:09:37ZGuchun Chenguchun.chen@amd.com2019-09-11T03:10:02Zurn:sha1:d7b1ed4ac3fc08a1b29be3a9f09b12a8a969d9d0
These registers will be accessed for querying ras errors.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: update nbio v7_4 ip header files2019-09-13T22:11:04ZHawking ZhangHawking.Zhang@amd.com2019-06-05T06:20:38Zurn:sha1:fc098fb4ed0c0ff49d50ffe314649181acd74f81
Add mmBIF_INTR_CNTL and its shift mask.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>