<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/amd/include/asic_reg/smu, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/smu?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/smu?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2019-10-15T19:55:31Z</updated>
<entry>
<title>drm/amdgpu: add new SMU 7.1.3 registers for BACO</title>
<updated>2019-10-15T19:55:31Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-10-04T20:18:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5d934ac0d04c94d960f9310a6e20ced07a964bc9'/>
<id>urn:sha1:5d934ac0d04c94d960f9310a6e20ced07a964bc9</id>
<content type='text'>
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new SMU 7.1.2 registers for BACO</title>
<updated>2019-10-15T19:55:31Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-10-04T20:16:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9fc00ea774693a4a13ec88c4bff7e199f987bfa1'/>
<id>urn:sha1:9fc00ea774693a4a13ec88c4bff7e199f987bfa1</id>
<content type='text'>
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add new SMU 7.0.1 registers for BACO</title>
<updated>2019-10-15T19:55:31Z</updated>
<author>
<name>Alex Deucher</name>
<email>alexander.deucher@amd.com</email>
</author>
<published>2019-10-04T20:14:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c74c524e7c41e508c186173ec62ec8fc0a93165f'/>
<id>urn:sha1:c74c524e7c41e508c186173ec62ec8fc0a93165f</id>
<content type='text'>
Reviewed-by: Evan Quan &lt;evan.quan@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/pp: Export registers for read vddc on VI/Vega10</title>
<updated>2018-02-19T19:17:49Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2018-01-02T06:06:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=680731ade574e770e16f4488eb4217e8b8b13ffe'/>
<id>urn:sha1:680731ade574e770e16f4488eb4217e8b8b13ffe</id>
<content type='text'>
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add CI asics support to smumgr (v3)</title>
<updated>2017-09-26T17:06:57Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-09-08T11:34:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9f4b35411cfed96d4f9f092b2fed14905af84d89'/>
<id>urn:sha1:9f4b35411cfed96d4f9f092b2fed14905af84d89</id>
<content type='text'>
This ports support for CI asics (Bonaire, Hawaii)
to the powerplay smumgr

v2: warning fix (Alex)
v3: squash in fix for thermal (Tom)

Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/powerplay: add a new register define for APU in VI.</title>
<updated>2017-03-30T03:54:06Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-03-17T08:21:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=1c622002b1aae6bf97be6f3c36203a61d8cc61cb'/>
<id>urn:sha1:1c622002b1aae6bf97be6f3c36203a61d8cc61cb</id>
<content type='text'>
the ixcurrent_pg_status addr is different between APU and DGPU.

Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: read hw register to check pg status.</title>
<updated>2017-02-13T17:43:04Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-02-08T09:17:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=254cd2e08dd0c44f9de6424f10390343a34b4f5a'/>
<id>urn:sha1:254cd2e08dd0c44f9de6424f10390343a34b4f5a</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu: add current_pg_status register define for smu7.1</title>
<updated>2017-02-08T22:20:22Z</updated>
<author>
<name>Rex Zhu</name>
<email>Rex.Zhu@amd.com</email>
</author>
<published>2017-01-25T04:17:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cbd9262f80e71088c8758464f52a38c3c0299ff8'/>
<id>urn:sha1:cbd9262f80e71088c8758464f52a38c3c0299ff8</id>
<content type='text'>
Signed-off-by: Rex Zhu &lt;Rex.Zhu@amd.com&gt;
Acked-by: Christian König &lt;christian.koenig@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amd/amdgpu: Introduction of SI registers (v2)</title>
<updated>2016-11-11T15:21:07Z</updated>
<author>
<name>Tom St Denis</name>
<email>tom.stdenis@amd.com</email>
</author>
<published>2016-10-26T15:58:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33'/>
<id>urn:sha1:de2bdb3dcf9228030b4e0a2d83f3d6b6bedc6c33</id>
<content type='text'>
This introduces the SI registers in the amdgpu
driver style.

v2: squash duplicates fix

Signed-off-by: Tom St Denis &lt;tom.stdenis@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
<entry>
<title>drm/amdgpu:use smc_index_11 for VI</title>
<updated>2016-10-25T18:38:20Z</updated>
<author>
<name>Monk Liu</name>
<email>Monk.Liu@amd.com</email>
</author>
<published>2016-03-29T03:01:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4bc10d168a419dc07194fdb93ccc4c8cad1788e4'/>
<id>urn:sha1:4bc10d168a419dc07194fdb93ccc4c8cad1788e4</id>
<content type='text'>
for VI smc, index_0 to index_8 are all not safe,
they may used by BIOS/FW, and index_11 is reserved
only for driver.

Signed-off-by: Monk Liu &lt;Monk.Liu@amd.com&gt;
Reviewed-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
Signed-off-by: Alex Deucher &lt;alexander.deucher@amd.com&gt;
</content>
</entry>
</feed>
