Linux kernel development work - see feature branches https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/smuio?h=master 2022-05-04T13:54:35Z 2022-05-04T13:54:35Z Hawking Zhang Hawking.Zhang@amd.com 2021-12-30T11:25:29Z urn:sha1:55437d3bf4d51a321a81551c8750a5dd5d5c1322 Add smuio v13_0_6 register offset and shift masks header files (Hawking) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-03-10T05:01:06Z Hawking Zhang Hawking.Zhang@amd.com 2020-12-07T12:32:28Z urn:sha1:be547828c0649eef0abb0662403d8f506aed774c v1: Add smuio v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up smuio v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2021-02-09T20:28:11Z Likun Gao Likun.Gao@amd.com 2021-02-03T10:21:52Z urn:sha1:2a53291ef2e607d449f60a3f11d1861a9671b8dd Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2020-04-01T18:44:43Z Tom St Denis tom.stdenis@amd.com 2020-03-25T19:07:01Z urn:sha1:ba56657d187ac77afa1063334fe2e28b3aebbf74 The PWR block was merged into the SMUIO block by revision 12 so we add that to the smuio_12_0_0 headers. (v2): Drop nonsensical smuio_10_0_0 header Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2020-04-01T18:44:43Z Tom St Denis tom.stdenis@amd.com 2020-03-25T13:33:29Z urn:sha1:2e40d9b915d4b95ea9eb7de471fe76267ddf31e8 This register is needed by umr. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2019-10-03T14:11:03Z Kent Russell kent.russell@amd.com 2019-09-23T01:20:14Z urn:sha1:3f94281751dcb15dcac23f218f30ddbfd8c34f4b These are the offsets for CKSVII2C1, and match up with the values already added for CKSVII2C v2: Don't remove some of the CSKVII2C values Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2019-08-27T13:17:27Z Andrey Grodzovsky andrey.grodzovsky@amd.com 2019-04-30T17:58:56Z urn:sha1:6a3068065fa4d6f931a12573d4bda5d85261cee2 v3: Merge CKSVII2C_IC regs into exsisting headers. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2019-06-20T20:54:44Z Hawking Zhang Hawking.Zhang@amd.com 2019-03-03T03:32:16Z urn:sha1:d2996831b288953505c72be9b0b75b26621f186a Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2018-10-09T21:45:58Z Evan Quan evan.quan@amd.com 2018-09-17T10:41:28Z urn:sha1:42fae99520090423ad639af889d7376774df7fdf Export the correct gfx voltage by hwmon interface. V2: update the register naming for consistency Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 2018-02-19T19:17:49Z Rex Zhu Rex.Zhu@amd.com 2018-01-02T06:06:05Z urn:sha1:680731ade574e770e16f4488eb4217e8b8b13ffe Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>