linux-dev/drivers/gpu/drm/amd/include/asic_reg/vcn, branch masterLinux kernel development work - see feature brancheshttps://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/amd/include/asic_reg/vcn?h=master2022-05-04T14:43:55Zdrm/amdgpu: add vcn 4_0_0 header files v72022-05-04T14:43:55ZLeo Liuleo.liu@amd.com2021-12-30T11:34:16Zurn:sha1:ed1db32e33ed534fbb914f4e4b5fb7b54448f295
Add VCN 4.0.0 registers
Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/vcn: Add vcn and jpeg ver 2.6 ras register definition2022-03-28T16:54:39ZMohammad Zafar ZiyaMohammadzafar.ziya@amd.com2022-03-23T02:54:15Zurn:sha1:f0a339a8c0963abc80640975585df469e27ba3df
Adding vcn and jpeg ver 2.6 ras register definition
Signed-off-by: Mohammad Zafar Ziya <Mohammadzafar.ziya@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add vcn v2_6_0 ip headers (v3)2021-03-10T05:01:20ZHawking ZhangHawking.Zhang@amd.com2020-12-07T12:37:25Zurn:sha1:b77a9fdf526b8eca954d8f11a93847ddb65168d8
v1: Add vcn v2_6_0 register offset and
shift masks in header files (Hawking)
v2: Clean up vcn v2_6_0 registers (Alex)
v3: update registers (Alex)
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN 3.0 AV1 registers2020-09-18T03:05:57ZAlex Deucheralexander.deucher@amd.com2020-05-01T20:45:09Zurn:sha1:1b51916b9734acd609c4f552e582cdc59ac254d6
This adds the AV1 registers.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN3.0 register headers (v2)2020-06-03T17:51:55ZLeo Liuleo.liu@amd.com2019-08-13T14:01:47Zurn:sha1:a5a2597771c3f53562cd200c67135835f945233c
Sienna_Cichlid VCN headers
v2: squash in updates (Alex)
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN0 and VCN1 needed headers2019-10-25T20:50:09ZJane Jianjane.jian@amd.com2019-10-17T15:30:20Zurn:sha1:6aec5bb4892a2c4881261532e99eef86e5f1c734
Add mmsch part registers
Signed-off-by: Jane Jian <jane.jian@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN2.5 headers2019-07-18T19:18:01ZLeo Liuleo.liu@amd.com2019-03-21T13:08:19Zurn:sha1:c54a60db0d722413628b8d6c4c480c7ac1238428
VCN is the multi-media block.
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu: add VCN 2.0 register headers2019-06-20T20:54:33ZHawking ZhangHawking.Zhang@amd.com2019-03-03T03:23:35Zurn:sha1:326354fa97cf0aa97e292c81f2e8e21636283b80
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headers2019-03-19T20:36:48ZTom St Denistom.stdenis@amd.com2019-03-04T15:58:44Zurn:sha1:054d282d179eba78012a26dbd4e4f1b231c596f1
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amdgpu/vcn:Add new register offset/mask for VCN2018-10-12T17:53:52ZJames ZhuJames.Zhu@amd.com2018-10-02T18:38:18Zurn:sha1:b53d3049d258fe731ebc510cd631ceffc7abfc91
Add new register offset/mask for VCN to support
latest VCN implementation.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>