linux-dev/drivers/gpu/drm/amd/pm/powerplay, branch linus/master

Backmerge tag 'v5.18-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into drm-next

2022-05-03T06:08:48Z

Linux 5.18-rc5 There was a build fix for arm I wanted in drm-next, so backmerge rather then cherry-pick. Signed-off-by: Dave Airlie

drm/amd/pm: fix the deadlock issue observed on SI

2022-04-27T21:38:02Z

The adev->pm.mutx is already held at the beginning of amdgpu_dpm_compute_clocks/amdgpu_dpm_enable_uvd/amdgpu_dpm_enable_vce. But on their calling path, amdgpu_display_bandwidth_update will be called and thus its sub functions amdgpu_dpm_get_sclk/mclk. They will then try to acquire the same adev->pm.mutex and deadlock will occur. By placing amdgpu_display_bandwidth_update outside of adev->pm.mutex protection(considering logically they do not need such protection) and restructuring the call flow accordingly, we can eliminate the deadlock issue. This comes with no real logics change. Fixes: 3712e7a49459 ("drm/amd/pm: unified lock protections in amdgpu_dpm.c") Reported-by: Paul Menzel Reported-by: Arthur Marsh Link: https://lore.kernel.org/all/9e689fea-6c69-f4b0-8dee-32c4cf7d8f9c@molgen.mpg.de/ BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1957 Signed-off-by: Evan Quan Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher

drm/amdgpu/smu10: fix SoC/fclk units in auto mode

2022-04-06T16:02:57Z

SMU takes clock limits in Mhz units. socclk and fclk were using 10 khz units in some cases. Switch to Mhz units. Fixes higher than required SoC clocks. Fixes: 97cf32996c46d9 ("drm/amd/pm: Removed fixed clock in auto mode DPM") Reviewed-by: Paul Menzel Signed-off-by: Alex Deucher Cc: stable@vger.kernel.org

drm/amdgpu/smu10: fix SoC/fclk units in auto mode

2022-04-06T14:20:45Z

amdgpu/pm: Implement emit_clk_levels for vega10

2022-03-28T16:54:32Z

(v1) - implement emit_clk_levels for vega10, based on print_clk_levels, but using sysfs_emit rather than sprintf - modify local int vars to use uint32_t to match arg type of called functions - add return of error codes - refactor OD_XXX cases to return early with -EOPNOTSUPP if !(hwmgr->od_enabled) Signed-off-by: Darren Powell Reviewed-by: Evan Quan Signed-off-by: Alex Deucher

amdgpu/pm: Add new hwmgr API function "emit_clock_levels"

2022-03-28T16:54:22Z

Extend commit 7f36948c92b2 ("amdgpu/pm: Implement new API function "emit" that accepts buffer base and write offset") Add new hwmgr API function "emit_clock_levels" - add member emit_clock_levels to pp_hwmgr_func - Implemented pp_dpm_emit_clock_levels - add pp_dpm_emit_clock_levels to pp_dpm_funcs Signed-off-by: Darren Powell Reviewed-by: Evan Quan Signed-off-by: Alex Deucher

gpu/amd: vega10_hwmgr: fix inappropriate private variable name

2022-03-02T23:40:05Z

In file vega10_hwmgr.c, the names of struct vega10_power_state * and struct pp_power_state * are confusingly used, which may lead to some confusion. Status quo is that variables of type struct vega10_power_state * are named "vega10_ps", "ps", "vega10_power_state". A more appropriate usage is that struct are named "ps" is used for variabled of type struct pp_power_state *. So rename struct vega10_power_state * which are named "ps" and "vega10_power_state" to "vega10_ps", I also renamed "psa" to "vega10_psa" and "psb" to "vega10_psb" to make it more clearly. The rows longer than 100 columns are involved. Reviewed-by: Evan Quan Signed-off-by: Meng Tang Signed-off-by: Alex Deucher

drm/amd: smu7: downgrade voltage error to info

2022-02-16T22:30:02Z

The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162 Reviewed-by: Alex Deucher Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher

drm/amd: Expose the FRU SMU I2C bus

2022-01-27T20:49:48Z

Expose both SMU I2C buses. Some boards use the same bus for both the RAS and FRU EEPROMs and others use different buses. This enables the additional I2C bus and sets the right buses to use for RAS and FRU EEPROM access. Cc: Roy Sun Co-developed-by: Alex Deucher Signed-off-by: Luben Tuikov Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher

drm/amdgpu/pm/smu7: drop message about VI performance levels

2022-01-25T23:00:36Z

Earlier chips only had two performance levels, but newer ones potentially had more. The message is harmless. Drop the message to avoid spamming the log. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1874 Reviewed-by: Evan Quan Signed-off-by: Alex Deucher