Linux kernel development work - see feature branches https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/msm/dsi/dsi.xml.h?h=linus%2Fmaster 2022-04-25T21:56:22Z 2022-04-25T21:56:22Z Vinod Koul vkoul@kernel.org 2022-04-06T09:40:30Z urn:sha1:83527af2eb457d7cd7e2119a311f04f505160f9c Update headers from mesa commit: commit 28ae397be111c37c6ced397e12d453a7695701bd Author: Vinod Koul <vkoul@kernel.org> Date: Fri Apr 1 16:53:04 2022 +0530 freedreno/registers: update dsi registers to support dsc Display Stream compression (DSC) compresses the display stream in host which is later decoded by panel. This requires addition of 3 new DSI registers to support DSC over DSI. Signed-off-by: Vinod Koul <vkoul@kernel.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14967> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Patchwork: https://patchwork.freedesktop.org/patch/480932/ Link: https://lore.kernel.org/r/20220406094031.1027376-14-vkoul@kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> 2022-03-04T19:50:41Z Rob Clark robdclark@chromium.org 2022-03-04T00:52:14Z urn:sha1:57cfe41c5f50aaad92942ff9947c6cee54b9d314 Update headers from mesa commit: commit 7e63fa2bb13cf14b765ad06d046789ee1879b5ef Author: Rob Clark <robclark@freedesktop.org> AuthorDate: Wed Mar 2 17:11:10 2022 -0800 freedreno/registers: Add a couple regs we need for kernel Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15221> Signed-off-by: Rob Clark <robdclark@chromium.org> [for display bits:] Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Link: https://lore.kernel.org/r/20220304005317.776110-2-robdclark@gmail.com 2021-08-10T22:30:32Z Dmitry Baryshkov dmitry.baryshkov@linaro.org 2021-08-05T17:08:17Z urn:sha1:858c595a3f5d66db1ed003fdefef374ea4a8c961 Unlike previous generations, 7nm PHYs are required to collaborate with the host for continuos clock mode. Add changes neccessary to enable continuous clock mode in the 7nm DSI PHYs. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210805170817.3337665-1-dmitry.baryshkov@linaro.org [Fix merge conflict, and $description typo] Signed-off-by: Rob Clark <robdclark@chromium.org> 2021-08-07T18:48:39Z Abhinav Kumar abhinavk@codeaurora.org 2021-07-22T02:50:31Z urn:sha1:24a5993e5bc2b43673a3547b9ff96615421738f2 Update the DSI controller header XML file to add registers and bitfields to support rectangular checkered pattern generator. Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Link: https://lore.kernel.org/r/1626922232-29105-1-git-send-email-abhinavk@codeaurora.org Reviewed-by: Stephen Boyd <swboyd@chromium.org> [DB: removed headergen commit changes] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Rob Clark <robdclark@chromium.org> 2021-06-23T14:33:54Z Rob Clark robdclark@chromium.org 2021-05-30T22:44:23Z urn:sha1:cc4c26d4ae4e458669d46ff69f16ac0c74f7cd49 Based on mesa commit daa2ccff7a0201941db3901780d179e2634057d5 Small bit of .c churn in the phy code to adapt to split up of phy related registers. Signed-off-by: Rob Clark <robdclark@chromium.org> 2020-09-12T16:59:58Z Jonathan Marek jonathan@marek.ca 2020-09-11T15:09:39Z urn:sha1:1ef7c99d145c2759308e53bf19f2cc971677680c This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250. Implementation is based on 10nm driver, but updated based on the downstream 7nm driver. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> (SM8250) Signed-off-by: Rob Clark <robdclark@chromium.org> 2020-07-31T13:46:16Z Rob Clark robdclark@chromium.org 2020-07-07T20:34:59Z urn:sha1:c28c82e9db8584b15ae3754dfd80385949938a8b We haven't sync'd for a while.. pull in updates to get definitions for some fields in pkt7 payloads. Signed-off-by: Rob Clark <robdclark@chromium.org> Acked-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org> 2018-08-10T22:49:18Z Rob Clark robdclark@gmail.com 2018-08-06T18:57:14Z urn:sha1:2d756322533322650f4476265ba413498e998b56 Resync generated headers to pull in a6xx registers. Signed-off-by: Rob Clark <robdclark@gmail.com> 2018-02-20T15:41:20Z Archit Taneja architt@codeaurora.org 2018-01-17T06:05:24Z urn:sha1:6d5796af7136046835621ffe680eb15ce88500b6 Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com> 2017-06-16T15:16:07Z Rob Clark robdclark@gmail.com 2017-06-16T12:57:18Z urn:sha1:52260ae4c461538a4f104d463a55dfc13c3d8543 Signed-off-by: Rob Clark <robdclark@gmail.com>