Linux kernel development work - see feature branches https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/nouveau/nvkm/subdev/mc?h=master 2021-06-03T11:29:45Z 2021-06-03T11:29:45Z Lee Jones lee.jones@linaro.org 2021-06-02T14:32:49Z urn:sha1:8c69d0298fb56f603e694cf0188e25b58dfe8b7e Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c:50:1: warning: no previous prototype for ‘tu102_mc_intr_unarm’ [-Wmissing-prototypes] drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c:62:1: warning: no previous prototype for ‘tu102_mc_intr_rearm’ [-Wmissing-prototypes] drivers/gpu/drm/nouveau/nvkm/subdev/mc/tu102.c:74:1: warning: no previous prototype for ‘tu102_mc_intr_mask’ [-Wmissing-prototypes] Cc: Ben Skeggs <bskeggs@redhat.com> Cc: David Airlie <airlied@linux.ie> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Alistair Popple <apopple@nvidia.com> Cc: dri-devel@lists.freedesktop.org Cc: nouveau@lists.freedesktop.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20210602143300.2330146-16-lee.jones@linaro.org 2021-02-11T01:50:04Z Ben Skeggs bskeggs@redhat.com 2021-01-16T06:17:21Z urn:sha1:26fbb4c8c7c3ee9a4c3b4de555a8587b5a19154e Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2021-02-11T01:49:54Z Ben Skeggs bskeggs@redhat.com 2021-02-06T00:54:34Z urn:sha1:209ec1b8412971f84aa265cbf81672e01f28bbfc Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2021-02-11T01:49:54Z Ben Skeggs bskeggs@redhat.com 2021-02-06T00:47:48Z urn:sha1:a35047ba771461c3acef174445db35d3613d3c41 Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2021-02-11T01:49:54Z Ben Skeggs bskeggs@redhat.com 2021-02-06T00:44:15Z urn:sha1:6997ea13120f948e9ab21e803b75bf647fea2876 Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2021-02-11T01:49:54Z Ben Skeggs bskeggs@redhat.com 2021-02-04T07:59:28Z urn:sha1:c653ab8383bfc4b26c83a6094ca795dc6eb422d4 Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2021-02-11T01:49:54Z Ben Skeggs bskeggs@redhat.com 2020-12-04T02:28:41Z urn:sha1:1fc2fddfbc8c6908451c06025b992e228a65bfba Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2021-02-11T00:14:32Z Ben Skeggs bskeggs@redhat.com 2021-02-04T04:28:06Z urn:sha1:efe2a9eccd720d93d3ea6271bc5e2245344daadb This switches to using the subdev list for lookup, and otherwise should be a no-op aside from switching the function signatures. Callers will be transitioned to split type+inst individually. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Reviewed-by: Lyude Paul <lyude@redhat.com> 2021-01-29T06:49:12Z Alistair Popple apopple@nvidia.com 2020-10-30T02:36:42Z urn:sha1:c81a51f05389464b19c5e0f0d29fadd305d75a34 This is no longer needed now that tu102_mc_intr_stat has been updated to look at the correct top-level interrupt bits. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> 2021-01-29T06:49:12Z Alistair Popple apopple@nvidia.com 2020-10-30T02:36:41Z urn:sha1:c3cc12eaf511a8a47ade42f521534255ef8ffd47 Turing reports MMU fault interrupts via new top level interrupt registers. The old PMC MMU interrupt vector is not used by the HW. This means we can remap the new top-level MMU interrupt to the exisiting PMC MMU bit which simplifies the implementation until all interrupts are moved over to using the new top level registers. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>