linux-dev/drivers/gpu/drm/tegra/dc.c, branch linus/master

drm/tegra: Support YVYU, VYUY and YU24 formats

2022-03-01T10:13:09Z

Signed-off-by: Thierry Reding

drm/tegra: Support semi-planar formats on Tegra114+

2022-03-01T10:13:09Z

The NV12, NV21, NV16, NV61, NV24 and NV42 formats are supported by Tegra114 and later display hardware. Add the necessary programming to allow them to be used. Note that this does not work for Tegra186 and later yet because those generations have a different display architecture that doesn't support the same formats. Signed-off-by: Thierry Reding

drm/tegra: Use dev_err_probe()

2022-02-24T16:03:08Z

Replace dev_printk() with a generic dev_err_probe() helper which silences noisy error messages about deferred probe and makes easy to debug failing deferred probe by printing notification about the failure to KMSG in the end of kernel booting process and by adding failing device and the reason of deferred probe to devices_deferred of debugfs. This was proven to be useful in the case of eDP driver regression by immediately showing why display driver was failing when user asked for help, otherwise it would've been much more difficult to debug such problems on a third party device that doesn't have developer setup. Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

drm/tegra: dc: Support OPP and SoC core voltage scaling

2021-12-16T13:07:07Z

Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on pre-Tegra186 SoCs. Reviewed-by: Ulf Hansson Tested-by: Peter Geis # Ouya T30 Tested-by: Paul Fertser # PAZ00 T20 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar # Ouya T30 Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

drm/tegra: dc: rgb: Allow changing PLLD rate on Tegra30+

2021-12-16T13:07:07Z

Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI bridge that requires a precise clock rate in order to operate properly. Tegra30 has a dedicated PLL for each display controller, hence the PLL rate can be changed freely. Allow PLL rate changes on Tegra30+ for RGB output. Configure the clock rate before display controller is enabled since DC itself may be running off this PLL and it's not okay to change the rate of the active PLL that doesn't support dynamic frequency switching since hardware will hang. Tested-by: Maxim Schwalm #TF700T Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

drm/tegra: dc: rgb: Move PCLK shifter programming to CRTC

2021-12-16T13:07:06Z

Asus TF700T tablet uses TC358768 DPI->DSI bridge that sits between Tegra's DPI output and display panel input. Bridge requires to have stable PCLK output before RGB encoder is enabled because it uses PCLK by itself to clock internal logic and bridge is programmed before Tegra's encoder is enabled. Hence the PCLK clock shifter must be programmed when CRTC is enabled, otherwise clock is unstable and bridge hangs because of it. Move the shifter programming from RGB encoder into CRTC. Tested-by: Maxim Schwalm #TF700T Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

drm/tegra: Support asynchronous commits for cursor

2021-12-16T13:07:06Z

This adds support for asynchronously updating the cursor plane, which enables support for the legacy cursor IOCTLs. Signed-off-by: Thierry Reding

drm/tegra: Do not reference tegra_plane_funcs directly

2021-12-16T13:07:06Z

Instead of referencing the tegra_plane_funcs struct directly, use each plane's vtable instead. This makes it more future-proof in case any of the planes ever use a different set of functions. Signed-off-by: Thierry Reding

drm/tegra: dc: Remove unused variables

2021-09-16T16:06:50Z

Remove unused variables from tegra_crtc_update_memory_bandwidth(). Fixes: 04d5d5df9df7 ("drm/tegra: dc: Support memory bandwidth management") Reported-by: kernel test robot Signed-off-by: Dmitry Osipenko Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding

drm/tegra: dc: Extend debug stats with total number of events

2021-08-13T10:31:07Z

It's useful to know the total number of underflow events and currently the debug stats are getting reset each time CRTC is being disabled. Let's account the overall number of events that doesn't get a reset. Reviewed-by: Michał Mirosław Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding