Linux kernel development work - see feature branches https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/tegra/dc.h?h=linus%2Fmaster 2022-03-01T10:13:09Z 2022-03-01T10:13:09Z Thierry Reding treding@nvidia.com 2022-02-24T18:39:51Z urn:sha1:cf5086d35d8c7c2b9cb1ca34590097a5f2f8b588 Signed-off-by: Thierry Reding <treding@nvidia.com> 2022-03-01T10:13:09Z Thierry Reding treding@nvidia.com 2022-01-12T08:36:29Z urn:sha1:a649b133c3154f3d1d297cf85711957e61c0f070 The NV12, NV21, NV16, NV61, NV24 and NV42 formats are supported by Tegra114 and later display hardware. Add the necessary programming to allow them to be used. Note that this does not work for Tegra186 and later yet because those generations have a different display architecture that doesn't support the same formats. Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-12-16T13:07:07Z Dmitry Osipenko digetx@gmail.com 2021-11-30T23:23:18Z urn:sha1:4ce3048c0a622978436e04b47eade8c45e1e8a75 Add OPP and SoC core voltage scaling support to the display controller driver. This is required for enabling system-wide DVFS on pre-Tegra186 SoCs. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-12-16T13:07:07Z Dmitry Osipenko digetx@gmail.com 2021-09-29T22:28:05Z urn:sha1:0c921b6d4ba06bc899fd84d3ce1c1afd3d00bc1c Asus Transformer TF700T is a Tegra30 tablet device which uses RGB->DSI bridge that requires a precise clock rate in order to operate properly. Tegra30 has a dedicated PLL for each display controller, hence the PLL rate can be changed freely. Allow PLL rate changes on Tegra30+ for RGB output. Configure the clock rate before display controller is enabled since DC itself may be running off this PLL and it's not okay to change the rate of the active PLL that doesn't support dynamic frequency switching since hardware will hang. Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-09-16T16:06:50Z Dmitry Osipenko digetx@gmail.com 2021-08-17T02:01:51Z urn:sha1:71eabafac1eb67d590d4500eaf38177537ea6d4a Remove unused variables from tegra_crtc_update_memory_bandwidth(). Fixes: 04d5d5df9df7 ("drm/tegra: dc: Support memory bandwidth management") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-13T10:31:07Z Dmitry Osipenko digetx@gmail.com 2021-06-01T04:21:08Z urn:sha1:ad85b0843ee4536593415ca890d7fb52cd7f1fbe It's useful to know the total number of underflow events and currently the debug stats are getting reset each time CRTC is being disabled. Let's account the overall number of events that doesn't get a reset. Reviewed-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-08-13T10:30:33Z Dmitry Osipenko digetx@gmail.com 2021-06-01T04:21:07Z urn:sha1:04d5d5df9df79f9045e76404775fc8a084aac23d Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory Controller drivers provide facility for memory bandwidth management via interconnect API. Let's wire up the interconnect API support to the DC driver in order to fix the distorted display output on T30 Ouya, T124 TK1 and other Tegra devices. Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30 Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30 Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124 Signed-off-by: Dmitry Osipenko <digetx@gmail.com> [treding@nvidia.com: unbreak Tegra186+ display support] Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-05-31T12:30:11Z Thierry Reding treding@nvidia.com 2021-05-27T18:27:21Z urn:sha1:ecc583e22d4689e38a528a8bf841ba1ce58edd7b Parameterize code in several places to allow scaling of windows. Note that this currently still relies on static programming of the various metering and memory pool allocation registers. This seems to work for the common cases, but may eventually need to be updated to support use-cases with multiple windows and higher bandwidth and latency requirements. Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-05-31T12:30:11Z Thierry Reding treding@nvidia.com 2021-05-27T18:15:46Z urn:sha1:e16efff4e5f490ce34a8c60d9ae7297dca5eb616 The driver currently exposes several YUV formats but fails to properly program all the registers needed to display such formats. Add the right programming sequences so that overlay windows can be used to accelerate color format conversions in multimedia playback use-cases. Signed-off-by: Thierry Reding <treding@nvidia.com> 2021-03-31T15:42:14Z Thierry Reding treding@nvidia.com 2021-03-26T14:51:39Z urn:sha1:7b6f846785f41d57917e36851c120cfbe87f0809 Tegra194 has a special physical address bit that enables some memory swizzling logic to support different sector layouts. Support the bit that selects the sector layout which is passed in the framebuffer modifier. Signed-off-by: Thierry Reding <treding@nvidia.com>