linux-dev/drivers/gpu/drm/tegra/dp.h, branch linus/masterLinux kernel development work - see feature brancheshttps://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/tegra/dp.h?h=linus%2Fmaster2019-10-28T10:18:53Zdrm/tegra: dp: Add DisplayPort link training helper2019-10-28T10:18:53ZThierry Redingtreding@nvidia.com2015-07-07T19:21:48Zurn:sha1:078c445733c1e8092e23391b251cad6b12f6156e
Add a helper that will perform link training as described in the
DisplayPort specification.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Add support for eDP link rates2019-10-28T10:18:53ZThierry Redingtreding@nvidia.com2018-02-01T16:46:42Zurn:sha1:6a127160c4883abf3a54d97024eda8118849fd5c
Parses additional link rates from DPCD if the sink supports eDP 1.4.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Add drm_dp_link_choose() helper2019-10-28T10:18:52ZThierry Redingtreding@nvidia.com2015-07-21T14:38:11Zurn:sha1:01f09f242eb5cb194a88cef669a099fa10fcb3f0
This helper chooses an appropriate configuration, according to the
bitrate requirements of the video mode and the capabilities of the
DisplayPort sink.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read AUX read interval from DPCD2019-10-28T10:18:52ZThierry Redingtreding@nvidia.com2015-07-07T19:01:26Zurn:sha1:ad7f2dda38911698deb2cc9ea45362f9a127e3f4
Store the AUX read interval from DPCD, so that it can be used to wait
for the durations given in the specification during link training.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read eDP version from DPCD2019-10-28T10:18:45ZThierry Redingtreding@nvidia.com2015-07-07T18:59:22Zurn:sha1:7aa3cc540d00b0be7d225202fa5c2d0c8e99f3f1
If the sink supports eDP, read the eDP revision from it's DPCD.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read alternate scrambler reset capability from sink2019-10-28T10:18:45ZThierry Redingtreding@nvidia.com2018-02-05T14:16:18Zurn:sha1:4ff9ba5674d16857372b936a8d08920a9851d1cd
Parse from the sink capabilities whether or not the eDP alternate
scrambler reset value of 0xfffe is supported.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read channel coding capability from sink2019-10-28T10:18:45ZThierry Redingtreding@nvidia.com2018-02-05T13:07:57Zurn:sha1:6c651b13e436030f996bcfb2f76833af94e44531
Parse from the sink capabilities whether or not it supports ANSI 8B/10B
channel coding as specified in ANSI X3.230-1994, clause 11.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read TPS3 capability from sink2019-10-28T10:18:45ZThierry Redingtreding@nvidia.com2015-07-07T18:52:07Zurn:sha1:db199502fa8b62afddde5379d94cac0439202111
The TPS3 capability can be exposed by DP 1.2 and later sinks if they
support the alternative training pattern for channel equalization.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Read fast training capability from link2019-10-28T10:18:44ZThierry Redingtreding@nvidia.com2015-12-03T12:07:43Zurn:sha1:cb072eebfa038361b4f578b65a205ad0abc6fe88
While probing the DisplayPort link, query the fast training capability.
If supported, drivers can use the fast link training sequence instead of
the more involved full link training sequence.
Signed-off-by: Thierry Reding <treding@nvidia.com>
drm/tegra: dp: Turn link capabilities into booleans2019-10-28T10:18:44ZThierry Redingtreding@nvidia.com2015-12-03T11:45:45Zurn:sha1:27ba465ce3397c4705f87c1f73e6d67c1b48ef0f
Rather than storing capabilities as flags in an integer, use a separate
boolean per capability. This simplifies the code that checks for these
capabilities.
Signed-off-by: Thierry Reding <treding@nvidia.com>