<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/gpu/drm/tegra/gr2d.c, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/tegra/gr2d.c?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/gpu/drm/tegra/gr2d.c?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2021-12-16T13:07:08Z</updated>
<entry>
<title>drm/tegra: Consolidate runtime PM management of older UAPI codepath</title>
<updated>2021-12-16T13:07:08Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=58ed47adcabb4ce13a60f56230074805957822fa'/>
<id>urn:sha1:58ed47adcabb4ce13a60f56230074805957822fa</id>
<content type='text'>
Move runtime PM management of older UAPI code paths into the common place.
This removes boilerplate code from client drivers.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gr2d: Support generic power domain and runtime PM</title>
<updated>2021-12-16T13:07:07Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e4e4a7104bd4cc753413bf56571cc99284d90bb4'/>
<id>urn:sha1:e4e4a7104bd4cc753413bf56571cc99284d90bb4</id>
<content type='text'>
Add runtime power management and support generic power domains.

Reviewed-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt; # Ouya T30
Tested-by: Paul Fertser &lt;fercerpav@gmail.com&gt; # PAZ00 T20
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt; # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar &lt;mattmerhar@protonmail.com&gt; # Ouya T30
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gr2d: Explicitly control module reset</title>
<updated>2021-12-16T13:07:07Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2021-07-08T14:37:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=271fca025a6d43f1c18a48543c5aaf31a31e4694'/>
<id>urn:sha1:271fca025a6d43f1c18a48543c5aaf31a31e4694</id>
<content type='text'>
As of commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling
clocks"), module resets are no longer automatically deasserted when the
module clock is enabled. To make sure that the gr2d module continues to
work, we need to explicitly control the module reset.

Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Cleanup and refcounting for syncpoints</title>
<updated>2021-03-31T15:42:13Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2021-03-29T13:38:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2aed4f5ab04af922a7cf1b616701845c9ed2473f'/>
<id>urn:sha1:2aed4f5ab04af922a7cf1b616701845c9ed2473f</id>
<content type='text'>
Add reference counting for allocated syncpoints to allow keeping
them allocated while jobs are referencing them. Additionally,
clean up various places using syncpoint IDs to use host1x_syncpt
pointers instead.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gr2d: Add compatible for Tegra114</title>
<updated>2021-01-15T16:19:09Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-01-12T18:14:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3ef170c25b974022b1ebec800e810fbc4b6fb06a'/>
<id>urn:sha1:3ef170c25b974022b1ebec800e810fbc4b6fb06a</id>
<content type='text'>
Tegra114 has GR2D hardware block, support it by the 2D driver.

Tested-by: Anton Bambura &lt;jenneron@protonmail.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gr2d: Correct swapped device-tree compatibles</title>
<updated>2021-01-15T16:18:52Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-01-12T18:14:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=efc8a109e5ce263be12f8f92c7ec8193b12b1d7b'/>
<id>urn:sha1:efc8a109e5ce263be12f8f92c7ec8193b12b1d7b</id>
<content type='text'>
The device-tree compatibles are swapped in the code, correct them.

Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt;
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Tested-by: Matt Merhar &lt;mattmerhar@protonmail.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: gr2d: Add tiled PATBASE address register</title>
<updated>2020-07-17T14:06:16Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-06-29T03:18:38Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5c9b969f699979981b1a2008cef76b56cf906f3e'/>
<id>urn:sha1:5c9b969f699979981b1a2008cef76b56cf906f3e</id>
<content type='text'>
There are two PATBASE address registers, one for linear layout and other
for tiled. The driver's address registers list misses the tiled PATBASE
register.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>gpu: host1x: Rename "parent" to "host"</title>
<updated>2020-01-10T15:37:38Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-12-02T09:51:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=608f43ad27ab26700677cc4d9ead3b2d9d338a21'/>
<id>urn:sha1:608f43ad27ab26700677cc4d9ead3b2d9d338a21</id>
<content type='text'>
Rename the host1x clients' parent to "host" because that more closely
describes what it is. The parent can be confused with the parent device
in terms of the device hierarchy. Subsequent patches will add a new
member that refers to the parent in that hierarchy.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Simplify IOMMU group selection</title>
<updated>2019-10-29T14:04:34Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-10-28T12:37:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7edd7961e58d531d19758134919de13dac47bcbe'/>
<id>urn:sha1:7edd7961e58d531d19758134919de13dac47bcbe</id>
<content type='text'>
All the devices that make up the DRM device are now part of the same
IOMMU group. This simplifies the handling of the IOMMU attachment and
also avoids exhausting the number of IOMMUs available on early Tegra
SoC generations.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>drm/tegra: Move IOMMU group into host1x client</title>
<updated>2019-10-28T10:18:37Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2019-02-08T13:35:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=aacdf19849734d1be5e407932228ae101ba5b92f'/>
<id>urn:sha1:aacdf19849734d1be5e407932228ae101ba5b92f</id>
<content type='text'>
Handling of the IOMMU group attachment is common to all clients, so move
the group into the client to simplify code.

Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
</feed>
