linux-dev/drivers/gpu/drm/tegra/plane.c, branch linus/master

drm/tegra: Support YVYU, VYUY and YU24 formats

2022-03-01T10:13:09Z

Signed-off-by: Thierry Reding

drm/tegra: Support semi-planar formats on Tegra114+

2022-03-01T10:13:09Z

The NV12, NV21, NV16, NV61, NV24 and NV42 formats are supported by Tegra114 and later display hardware. Add the necessary programming to allow them to be used. Note that this does not work for Tegra186 and later yet because those generations have a different display architecture that doesn't support the same formats. Signed-off-by: Thierry Reding

drm/tegra: Propagate errors from drm_gem_plane_helper_prepare_fb()

2021-12-16T13:07:06Z

Currently this function doesn't return an error, but that may change in the future, so make sure to propagate any error codes that it might return. Signed-off-by: Thierry Reding

drm/tegra: Implement buffer object cache

2021-12-16T13:07:06Z

This cache is used to avoid mapping and unmapping buffer objects unnecessarily. Mappings are cached per client and stay hot until the buffer object is destroyed. Signed-off-by: Thierry Reding

drm/tegra: Implement correct DMA-BUF semantics

2021-12-16T13:07:06Z

DMA-BUF requires that each device that accesses a DMA-BUF attaches to it separately. To do so the host1x_bo_pin() and host1x_bo_unpin() functions need to be reimplemented so that they can return a mapping, which either represents an attachment or a map of the driver's own GEM object. Signed-off-by: Thierry Reding

Merge drm/drm-next into drm-misc-next

2021-09-14T07:25:30Z

Kickstart new drm-misc-next cycle. Signed-off-by: Maxime Ripard

drm/tegra: Use fourcc_mod_is_vendor() helper

2021-08-16T10:19:21Z

Rather than open-coding the vendor extraction operation, use the newly introduced helper macro. Reviewed-by: Daniel Vetter Signed-off-by: Thierry Reding Link: https://patchwork.freedesktop.org/patch/msgid/20210610111236.3814211-3-thierry.reding@gmail.com

drm/tegra: dc: Support memory bandwidth management

2021-08-13T10:30:33Z

Display controller (DC) performs isochronous memory transfers, and thus, has a requirement for a minimum memory bandwidth that shall be fulfilled, otherwise framebuffer data can't be fetched fast enough and this results in a DC's data-FIFO underflow that follows by a visual corruption. The Memory Controller drivers provide facility for memory bandwidth management via interconnect API. Let's wire up the interconnect API support to the DC driver in order to fix the distorted display output on T30 Ouya, T124 TK1 and other Tegra devices. Tested-by: Peter Geis # Ouya T30 Tested-by: Matt Merhar # Ouya T30 Tested-by: Nicolas Chauvet # PAZ00 T20 and TK1 T124 Signed-off-by: Dmitry Osipenko [treding@nvidia.com: unbreak Tegra186+ display support] Signed-off-by: Thierry Reding

drm/tegra: hub: Fix YUV support

2021-05-31T12:30:11Z

The driver currently exposes several YUV formats but fails to properly program all the registers needed to display such formats. Add the right programming sequences so that overlay windows can be used to accelerate color format conversions in multimedia playback use-cases. Signed-off-by: Thierry Reding

drm/tegra: Support sector layout on Tegra194

2021-03-31T15:42:14Z

Tegra194 has a special physical address bit that enables some memory swizzling logic to support different sector layouts. Support the bit that selects the sector layout which is passed in the framebuffer modifier. Signed-off-by: Thierry Reding