linux-dev/drivers/gpu/host1x, branch master

gpu: host1x: Use the bitmap API to allocate bitmaps

2022-07-08T15:38:34Z

Use bitmap_zalloc()/bitmap_free() instead of hand-writing them. It is less verbose and it improves the semantic. While at it, remove a useless bitmap_zero() call. The bitmap is already zero'ed when allocated. Signed-off-by: Christophe JAILLET Signed-off-by: Thierry Reding

gpu: host1x: Generalize host1x_cdma_push_wide()

2022-07-08T15:36:26Z

host1x_cdma_push_wide() had the assumptions that the last parameter word was a NOP opcode, and that NOP opcodes could be used in all situations. Neither are true with the new job opcode sequence, so adjust the function to not have these assumptions, and instead place an early RESTART opcode when necessary to jump back to the beginning of the pushbuffer. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Initialize syncval in channel_submit()

2022-07-08T15:35:19Z

During the refactoring of channel_submit(), assignment of syncval was moved but it is also used in channel_submit(). Add this assignment back to channel_submit() as well. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Register context bus unconditionally

2022-07-08T14:31:24Z

Conditional registration is a problem for other subsystems which may unwittingly try to interact with host1x_context_device_bus_type in an uninitialised state on non-Tegra platforms. A look under /sys/bus on a typical system already reveals plenty of entries from enabled but otherwise irrelevant configs, so lets keep things simple and register our context bus unconditionally too. Signed-off-by: Robin Murphy Reviewed-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Use RESTART_W to skip timed out jobs on Tegra186+

2022-07-08T14:27:53Z

When MLOCK enforcement is enabled, the 0-word write currently done is rejected by the hardware outside of an MLOCK region. As such, on these chips, which also have the newer, more convenient RESTART_W opcode, use that instead to skip over the timed out job. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Add MLOCK release code on Tegra234

2022-07-08T14:27:53Z

With the full-featured opcode sequence using MLOCKs, we need to also unlock those MLOCKs in the event of a timeout. However, it turns out that on Tegra186/Tegra194, by default, we don't need to do this; furthermore, on Tegra234 it is much simpler to do; so only implement this on Tegra234 for the time being. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Rewrite job opcode sequence

2022-07-08T14:27:53Z

For new (Tegra186+) SoCs, use a new ('full-featured') job opcode sequence that is compatible with virtualization. In particular, the Host1x hardware in Tegra234 is more strict regarding the sequence, requiring ACQUIRE_MLOCK-SETCLASS-SETSTREAMID opcodes to occur in that sequence without gaps (except for SETPAYLOAD), so let's do it properly in one go now. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Tegra234 device data and headers

2022-07-08T14:27:52Z

Add device data and chip headers for Tegra234. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Program interrupt destinations on Tegra234

2022-07-08T14:27:52Z

On Tegra234, each Host1x VM has 8 interrupt lines. Each syncpoint can be configured with which interrupt line should be used for threshold interrupt, allowing for load balancing. For now, to keep backwards compatibility, just set all syncpoints to the first interrupt. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding

gpu: host1x: Allow reset to be missing

2022-07-08T14:27:52Z

Host1x on Tegra234 does not have a software-controllable reset line. As such, don't bail out if we don't find one in the device tree. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding