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<title>linux-dev/drivers/infiniband/hw/mlx5, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/infiniband/hw/mlx5?h=linus%2Fmaster</id>
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<updated>2022-05-27T04:08:40Z</updated>
<entry>
<title>Merge tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma</title>
<updated>2022-05-27T04:08:40Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-05-27T04:08:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=780d8ce7162818cfe03e9a5e23b3af192a1d37bc'/>
<id>urn:sha1:780d8ce7162818cfe03e9a5e23b3af192a1d37bc</id>
<content type='text'>
Pull rdma updates from Jason Gunthorpe:
 "Small collection of incremental improvement patches:

   - Minor code cleanup patches, comment improvements, etc from static
     tools

   - Clean the some of the kernel caps, reducing the historical stealth
     uAPI leftovers

   - Bug fixes and minor changes for rdmavt, hns, rxe, irdma

   - Remove unimplemented cruft from rxe

   - Reorganize UMR QP code in mlx5 to avoid going through the IB verbs
     layer

   - flush_workqueue(system_unbound_wq) removal

   - Ensure rxe waits for objects to be unused before allowing the core
     to free them

   - Several rc quality bug fixes for hfi1"

* tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: (67 commits)
  RDMA/rtrs-clt: Fix one kernel-doc comment
  RDMA/hfi1: Remove all traces of diagpkt support
  RDMA/hfi1: Consolidate software versions
  RDMA/hfi1: Remove pointless driver version
  RDMA/hfi1: Fix potential integer multiplication overflow errors
  RDMA/hfi1: Prevent panic when SDMA is disabled
  RDMA/hfi1: Prevent use of lock before it is initialized
  RDMA/rxe: Fix an error handling path in rxe_get_mcg()
  IB/core: Fix typo in comment
  RDMA/core: Fix typo in comment
  IB/hf1: Fix typo in comment
  IB/qib: Fix typo in comment
  IB/iser: Fix typo in comment
  RDMA/mlx4: Avoid flush_scheduled_work() usage
  IB/isert: Avoid flush_scheduled_work() usage
  RDMA/mlx5: Remove duplicate pointer assignment in mlx5_ib_alloc_implicit_mr()
  RDMA/qedr: Remove unnecessary synchronize_irq() before free_irq()
  RDMA/hns: Use hr_reg_read() instead of remaining roce_get_xxx()
  RDMA/hns: Use hr_reg_xxx() instead of remaining roce_set_xxx()
  RDMA/irdma: Add SW mechanism to generate completions on error
  ...
</content>
</entry>
<entry>
<title>Merge tag 'v5.18' into rdma.git for-next</title>
<updated>2022-05-24T15:40:28Z</updated>
<author>
<name>Jason Gunthorpe</name>
<email>jgg@nvidia.com</email>
</author>
<published>2022-05-24T15:40:28Z</published>
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<id>urn:sha1:a6f844da39af8046798ba5cadf92a0c54da80b26</id>
<content type='text'>
Following patches have dependencies.

Resolve the merge conflict in
drivers/net/ethernet/mellanox/mlx5/core/main.c by keeping the new names
for the fs functions following linux-next:

https://lore.kernel.org/r/20220519113529.226bc3e2@canb.auug.org.au/

Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Remove duplicate pointer assignment in mlx5_ib_alloc_implicit_mr()</title>
<updated>2022-05-19T18:57:52Z</updated>
<author>
<name>Daisuke Matsuda</name>
<email>matsuda-daisuke@fujitsu.com</email>
</author>
<published>2022-05-18T04:49:14Z</published>
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<id>urn:sha1:988d74deaa46a9c63d2061c270692d6e6192c6c1</id>
<content type='text'>
The pointer imr-&gt;umem is assigned twice. Fix this by removing the
redundant one.

Link: https://lore.kernel.org/r/20220518044914.1903125-1-matsuda-daisuke@fujitsu.com
Signed-off-by: Daisuke Matsuda &lt;matsuda-daisuke@fujitsu.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>net/mlx5: Lag, expose number of lag ports</title>
<updated>2022-05-10T05:54:00Z</updated>
<author>
<name>Mark Bloch</name>
<email>mbloch@nvidia.com</email>
</author>
<published>2022-03-01T15:42:01Z</published>
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<id>urn:sha1:34a30d7635a8e37275a7b63bec09035ed762969b</id>
<content type='text'>
Downstream patches will add support for hardware lag with
more than 2 ports. Add a way for users to query the number of lag ports.

Signed-off-by: Mark Bloch &lt;mbloch@nvidia.com&gt;
Reviewed-by: Maor Gottlieb &lt;maorg@nvidia.com&gt;
Signed-off-by: Saeed Mahameed &lt;saeedm@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Clean UMR QP type flow from mlx5_ib_post_send()</title>
<updated>2022-04-25T15:00:10Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@nvidia.com</email>
</author>
<published>2022-04-12T07:24:07Z</published>
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<id>urn:sha1:c8a02e38f86fbab30aab6261662076516cfb9ec3</id>
<content type='text'>
No internal UMR operation is using mlx5_ib_post_send(), remove the UMR QP
type logic from this function.

Link: https://lore.kernel.org/r/0b2f368f14bc9266ebdf92a601ca4e1e5b1e1188.1649747695.git.leonro@nvidia.com
Signed-off-by: Aharon Landau &lt;aharonl@nvidia.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Use mlx5_umr_post_send_wait() to update xlt</title>
<updated>2022-04-25T15:00:08Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@nvidia.com</email>
</author>
<published>2022-04-12T07:24:06Z</published>
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<id>urn:sha1:636bdbfc9996567af1a3ed89ecf92ea5028a8a89</id>
<content type='text'>
Move mlx5_ib_update_mr_pas logic to umr.c, and use
mlx5_umr_post_send_wait() instead of mlx5_ib_post_send_wait().

Since it is the last use of mlx5_ib_post_send_wait(), remove it.

Link: https://lore.kernel.org/r/55a4972f156aba3592a2fc9bcb33e2059acf295f.1649747695.git.leonro@nvidia.com
Signed-off-by: Aharon Landau &lt;aharonl@nvidia.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Use mlx5_umr_post_send_wait() to update MR pas</title>
<updated>2022-04-25T14:59:54Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@nvidia.com</email>
</author>
<published>2022-04-12T07:24:05Z</published>
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<id>urn:sha1:b3d47ebd490823514a2d637caee0870b6f192b07</id>
<content type='text'>
Move mlx5_ib_update_mr_pas logic to umr.c, and use
mlx5_umr_post_send_wait() instead of mlx5_ib_post_send_wait().

Link: https://lore.kernel.org/r/ed8f2ee6c64804072155d727149abf7105f92536.1649747695.git.leonro@nvidia.com
Signed-off-by: Aharon Landau &lt;aharonl@nvidia.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Move creation and free of translation tables to umr.c</title>
<updated>2022-04-25T14:58:42Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@nvidia.com</email>
</author>
<published>2022-04-12T07:24:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=916adb491e84bc8b130618e4969c1d196525abf2'/>
<id>urn:sha1:916adb491e84bc8b130618e4969c1d196525abf2</id>
<content type='text'>
The only use of the translation tables is to update the mkey translation
by a UMR operation. Move the responsibility of creating and freeing them
to umr.c

Link: https://lore.kernel.org/r/1d93f1381be82a22aaf1168cdbdfb227eac1ce62.1649747695.git.leonro@nvidia.com
Signed-off-by: Aharon Landau &lt;aharonl@nvidia.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Use mlx5_umr_post_send_wait() to rereg pd access</title>
<updated>2022-04-25T14:53:00Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@nvidia.com</email>
</author>
<published>2022-04-12T07:24:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=483196764091621b8dd45d7af29e7a9c874a9f19'/>
<id>urn:sha1:483196764091621b8dd45d7af29e7a9c874a9f19</id>
<content type='text'>
Move rereg_pd_access logic to umr.c, and use mlx5_umr_post_send_wait()
instead of mlx5_ib_post_send_wait().

Link: https://lore.kernel.org/r/18da4f47edbc2561f652b7ee4e7a5269e866af77.1649747695.git.leonro@nvidia.com
Signed-off-by: Aharon Landau &lt;aharonl@nvidia.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
<entry>
<title>RDMA/mlx5: Use mlx5_umr_post_send_wait() to revoke MRs</title>
<updated>2022-04-25T14:53:00Z</updated>
<author>
<name>Aharon Landau</name>
<email>aharonl@nvidia.com</email>
</author>
<published>2022-04-12T07:24:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=33e8aa8e049811de87cd1c16a2ead85e0c9f9606'/>
<id>urn:sha1:33e8aa8e049811de87cd1c16a2ead85e0c9f9606</id>
<content type='text'>
Move the revoke_mr logic to umr.c, and using mlx5_umr_post_send_wait()
instead of mlx5_ib_post_send_wait().

In the new implementation, do not zero out the access flags. Before
reusing the MR, we will update it to the required access.

Link: https://lore.kernel.org/r/63717dfdaf6007f81b3e6dbf598f5bf3875ce86f.1649747695.git.leonro@nvidia.com
Signed-off-by: Aharon Landau &lt;aharonl@nvidia.com&gt;
Reviewed-by: Michael Guralnik &lt;michaelgur@nvidia.com&gt;
Signed-off-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Signed-off-by: Jason Gunthorpe &lt;jgg@nvidia.com&gt;
</content>
</entry>
</feed>
