linux-dev/drivers/irqchip/Kconfig, branch linus/master

irqchip/xilinx: Remove microblaze+zynq dependency

2022-06-09T16:34:56Z

The Xilinx IRQ controller doesn't really have any architecture dependencies - it's a generic AXI component that can be used for any FPGA core from Zynq hard processor systems to microblaze+riscv soft cores and more. Signed-off-by: Jamie Iles Acked-by: Michal Simek Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220606213952.298686-1-jamie@jamieiles.com

irqchip: Adjust Kconfig for Loongson

2022-06-03T12:09:27Z

HTVEC will be shared by both MIPS-based and LoongArch-based Loongson processors (not only Loongson-3), so we adjust its description. HTPIC is only used by MIPS-based Loongson, so we add a MIPS dependency. Acked-by: Marc Zyngier Reviewed-by: WANG Xuerui Reviewed-by: Jiaxun Yang Signed-off-by: Huacai Chen

Merge tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic

2022-05-26T17:50:30Z

Pull asm-generic updates from Arnd Bergmann: "The asm-generic tree contains three separate changes for linux-5.19: - The h8300 architecture is retired after it has been effectively unmaintained for a number of years. This is the last architecture we supported that has no MMU implementation, but there are still a few architectures (arm, m68k, riscv, sh and xtensa) that support CPUs with and without an MMU. - A series to add a generic ticket spinlock that can be shared by most architectures with a working cmpxchg or ll/sc type atomic, including the conversion of riscv, csky and openrisc. This series is also a prerequisite for the loongarch64 architecture port that will come as a separate pull request. - A cleanup of some exported uapi header files to ensure they can be included from user space without relying on other kernel headers" * tag 'asm-generic-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: h8300: remove stale bindings and symlink sparc: add asm/stat.h to UAPI compile-test coverage powerpc: add asm/stat.h to UAPI compile-test coverage mips: add asm/stat.h to UAPI compile-test coverage riscv: add linux/bpf_perf_event.h to UAPI compile-test coverage kbuild: prevent exported headers from including , agpgart.h: do not include from exported header csky: Move to generic ticket-spinlock RISC-V: Move to queued RW locks RISC-V: Move to generic spinlocks openrisc: Move to ticket-spinlock asm-generic: qrwlock: Document the spinlock fairness requirements asm-generic: qspinlock: Indicate the use of mixed-size atomics asm-generic: ticket-lock: New generic ticket-based spinlock remove the h8300 architecture

irqchip: Add Kconfig symbols for sunxi drivers

2022-05-17T09:13:57Z

Not all of these drivers are needed on every ARCH_SUNXI platform. In particular, the ARCH_SUNXI symbol will be reused for the Allwinner D1, a RISC-V SoC which contains none of these irqchips. Introduce Kconfig symbols so we can select only the drivers actually used by a particular set of platforms. This also lets us move the irqchip driver dependencies to a more appropriate location. Signed-off-by: Samuel Holland Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220509034941.30704-1-samuel@sholland.org

irq/qcom-mpm: Fix build error without MAILBOX

2022-04-05T15:33:13Z

If MAILBOX is n, building fails: drivers/irqchip/irq-qcom-mpm.o: In function `mpm_pd_power_off': irq-qcom-mpm.c:(.text+0x174): undefined reference to `mbox_send_message' irq-qcom-mpm.c:(.text+0x174): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `mbox_send_message' Make QCOM_MPM depends on MAILBOX to fix this. Fixes: a6199bb514d8 ("irqchip: Add Qualcomm MPM controller driver") Signed-off-by: YueHaibing Acked-by: Shawn Guo Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220317131956.30004-1-yuehaibing@huawei.com

Merge branch 'remove-h8300' of git://git.infradead.org/users/hch/misc into asm-generic

2022-04-04T12:42:49Z

* 'remove-h8300' of git://git.infradead.org/users/hch/misc: remove the h8300 architecture This is clearly the least actively maintained architecture we have at the moment, and probably the least useful. It is now the only one that does not support MMUs at all, and most of the boards only support 4MB of RAM, out of which the defconfig kernel needs more than half just for .text/.data. Guenter Roeck did the original patch to remove the architecture in 2013 after it had already been obsolete for a while, and Yoshinori Sato brought it back in a much more modern form in 2015. Looking at the git history since the reinstantiation, it's clear that almost all commits in the tree are build fixes or cross-architecture cleanups: $ git log --no-merges --format=%an v4.5.. arch/h8300/ | sort | uniq -c | sort -rn | head -n 12 25 Masahiro Yamada 18 Christoph Hellwig 14 Mike Rapoport 9 Arnd Bergmann 8 Mark Rutland 7 Peter Zijlstra 6 Kees Cook 6 Ingo Molnar 6 Al Viro 5 Randy Dunlap 4 Yury Norov Signed-off-by: Arnd Bergmann

irqchip: Add Qualcomm MPM controller driver

2022-03-11T19:19:46Z

Qualcomm SoCs based on the RPM architecture have a MSM Power Manager (MPM) in always-on domain. In addition to managing resources during sleep, the hardware also has an interrupt controller that monitors the interrupts when the system is asleep, wakes up the APSS when one of these interrupts occur and replays it to GIC after it becomes operational. It adds an irqchip driver for this interrupt controller, and here are some notes about it. - For given SoC, a fixed number of MPM pins are supported, e.g. 96 pins on QCM2290. Each of these MPM pins can be either a MPM_GIC pin or a MPM_GPIO pin. The mapping between MPM_GIC pin and GIC interrupt is defined by SoC, as well as the mapping between MPM_GPIO pin and GPIO number. The former mapping is retrieved from device tree, while the latter is defined in TLMM pinctrl driver. - The power domain (PD) .power_off hook is used to notify RPM that APSS is about to power collapse. This requires MPM PD be the parent PD of CPU cluster. - When SoC gets awake from sleep mode, the driver will receive an interrupt from RPM, so that it can replay interrupt for particular polarity. Signed-off-by: Shawn Guo Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20220308080534.3384532-3-shawn.guo@linaro.org

remove the h8300 architecture

2022-02-23T07:52:50Z

Signed-off-by: Christoph Hellwig

Merge branch irq/mchp-eic into irq/irqchip-next

2021-10-25T08:04:24Z

* irq/mchp-eic: : . : New irqchip driver for the Microchip EIC block : . irqchip/mchp-eic: Fix return value check in mchp_eic_init() irqchip/mchp-eic: Add support for the Microchip EIC dt-bindings: microchip,eic: Add bindings for the Microchip EIC Signed-off-by: Marc Zyngier

irqchip/irq-bcm7120-l2: Switch to IRQCHIP_PLATFORM_DRIVER

2021-10-20T19:06:34Z

Allow the user selection and building of this interrupt controller driver as a module since it is used on ARM/ARM64 based systems as a second level interrupt controller hanging off the ARM GIC and is therefore loadable during boot. To avoid using of_irq_count() which is not exported towards module, switch the driver to use the platform_device provided by the irqchip platform driver code and resolve the number of interrupts using platform_irq_count(). Signed-off-by: Florian Fainelli Signed-off-by: Marc Zyngier Link: https://lore.kernel.org/r/20211020184859.2705451-11-f.fainelli@gmail.com