linux-dev/drivers/mailbox, branch master

mailbox: qcom-ipcc: flag IRQ NO_THREAD

2022-10-06T02:51:58Z

PREEMPT_RT forces qcom-ipcc's handler to be threaded with interrupts enabled, which triggers a warning in __handle_irq_event_percpu(): irq 173 handler irq_default_primary_handler+0x0/0x10 enabled interrupts WARNING: CPU: 0 PID: 77 at kernel/irq/handle.c:161 __handle_irq_event_percpu+0x4c4/0x4d0 Mark it IRQF_NO_THREAD to avoid running the handler in a threaded context with threadirqs or PREEMPT_RT enabled. Signed-off-by: Eric Chanudet Acked-by: Sebastian Andrzej Siewior Signed-off-by: Jassi Brar

mailbox: pcc: Fix spelling mistake "Plaform" -> "Platform"

2022-10-06T02:51:14Z

There is a spelling mistake in a pr_err message. Fix it. Signed-off-by: Colin Ian King Signed-off-by: Jassi Brar

mailbox: bcm-ferxrm-mailbox: Fix error check for dma_map_sg

2022-10-06T02:50:53Z

dma_map_sg return 0 on error, fix the error check, and return -EIO to caller. Fixes: dbc049eee730 ("mailbox: Add driver for Broadcom FlexRM ring manager") Signed-off-by: Jack Wang Signed-off-by: Jassi Brar

mailbox: qcom-apcs-ipc: add IPQ8074 APSS clock support

2022-10-06T02:50:01Z

IPQ8074 has the APSS clock controller utilizing the same register space as the APCS, so provide access to the APSS utilizing a child device like IPQ6018. IPQ6018 and IPQ8074 use the same controller and driver, so just utilize IPQ6018 match data for IPQ8074. Signed-off-by: Robert Marko Reviewed-by: Dmitry Baryshkov Signed-off-by: Jassi Brar

mailbox: mpfs: account for mbox offsets while sending

2022-10-06T02:48:38Z

The mailbox offset is not only used for receiving messages, but it is also used by messages sent to the system controller by Linux that have a payload, such as the "digital signature service". It is also overloaded by certain other services (reprogramming of the FPGA fabric, see Link:) to have a meaning other than the offset the system controller should read from. When the driver was written, no such services of the latter type were in use & those of the former used an offset of zero so this has gone un-noticed. Link: https://www.microsemi.com/document-portal/doc_download/1245815-polarfire-fpga-and-polarfire-soc-fpga-system-services-user-guide # Section 5.2 Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley Signed-off-by: Jassi Brar

mailbox: mpfs: fix handling of the reg property

2022-10-06T02:48:31Z

The "data" region of the PolarFire SoC's system controller mailbox is not one continuous register space - the system controller's QSPI sits between the control and data registers. Split the "data" reg into two parts: "data" & "control". Optionally get the "data" register address from the 3rd reg property in the devicetree & fall back to using the old base + MAILBOX_REG_OFFSET that the current code uses. Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley Signed-off-by: Jassi Brar

mailbox: imx: fix RST channel support

2022-10-06T02:46:36Z

Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated to include the CR register. Add the missed CR register to xcr array. Fixes: 82ab513baed5 ("mailbox: imx: support RST channel") Reported-by: Liu Ying Signed-off-by: Peng Fan Tested-by: Liu Ying # i.MX8qm/qxp MEK boards boot Signed-off-by: Jassi Brar

mailbox: apple: Implement poll_data() operation

2022-09-15T18:14:01Z

This allows clients running in atomic context to poll for messages to arrive. Signed-off-by: Hector Martin Signed-off-by: Russell King (Oracle) Signed-off-by: Jassi Brar

mailbox: apple: Implement flush() operation

2022-09-15T18:14:01Z

This allows clients to use the atomic-safe mailbox API style. Signed-off-by: Hector Martin Signed-off-by: Russell King (Oracle) Signed-off-by: Jassi Brar

Merge tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration

2022-08-08T17:19:40Z

Pull mailbox updates from Jassi Brar: - mtk: - use rx_callback instead of cmdq_task_cb - qcom: - add syscon const - add SM6375 compatible - imx: - enable RST channel - clear pending irqs * tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: imx: clear pending interrupts dt-bindings: mailbox: qcom-ipcc: Add SM6375 compatible mailbox: imx: support RST channel dt-bindings: mailbox: imx-mu: add RST channel dt-bindings: mailbox: qcom,apcs-kpss-global: Add syscon const for relevant entries mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb