media: v4l: cadence: Add Cadence MIPI-CSI2 TX driver

2018-05-17T10:22:08Z

The Cadence MIPI-CSI2 TX controller is an hardware block meant to be used as a bridge between pixel interfaces and a CSI-2 bus. It supports operating with an internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the latter case. While the virtual channel input on the pixel interface can be directly mapped to CSI2, the datatype input is actually a selection signal (3-bits) mapping to a table of up to 8 preconfigured datatypes/formats (programmed at start-up) The block supports up to 8 input datatypes. Acked-by: Benoit Parrot Reviewed-by: Niklas Söderlund Signed-off-by: Maxime Ripard Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab

media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver

2018-05-16T15:12:21Z

The Cadence CSI-2 RX Controller is an hardware block meant to be used as a bridge between a CSI-2 bus and pixel grabbers. It supports operating with internal or external D-PHY, with up to 4 lanes, or without any D-PHY. The current code only supports the latter case. It also support dynamic mapping of the CSI-2 virtual channels to the associated pixel grabbers, but that isn't allowed at the moment either. Acked-by: Benoit Parrot Reviewed-by: Niklas Söderlund Signed-off-by: Maxime Ripard Signed-off-by: Sakari Ailus Signed-off-by: Mauro Carvalho Chehab

linux-dev/drivers/media/platform/cadence/Makefile, branch master

media: v4l: cadence: Add Cadence MIPI-CSI2 TX driver

media: v4l: cadence: Add Cadence MIPI-CSI2 RX driver