<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/media/platform/verisilicon, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/media/platform/verisilicon?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/media/platform/verisilicon?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-09-24T07:01:15Z</updated>
<entry>
<title>media: hantro: Allows luma and chroma depth to be different</title>
<updated>2022-09-24T07:01:15Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@collabora.com</email>
</author>
<published>2022-08-29T16:21:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=39434d42e87fe23bff9f39d7b7485ad7764297d1'/>
<id>urn:sha1:39434d42e87fe23bff9f39d7b7485ad7764297d1</id>
<content type='text'>
Luma and chroma depth are set on different hardware registers.
Even if they aren't identical the bitstream can be compliant
to HEVC specifications and decoded by the hardware.

With this patch TSUNEQBD_A_MAIN10_Technicolor_2 conformance test
is successfully decoded.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@collabora.com&gt;
Reviewed-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>media: hantro: imx8m: Enable 10bit decoding</title>
<updated>2022-09-24T07:00:50Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@collabora.com</email>
</author>
<published>2022-08-29T16:21:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=dc39473d0340071bc04c07ba95c40f2bcf9f8ded'/>
<id>urn:sha1:dc39473d0340071bc04c07ba95c40f2bcf9f8ded</id>
<content type='text'>
Expose 10bit pixel formats to enable 10bit decoding in IMX8M SoCs.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@collabora.com&gt;
Reviewed-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>media: Hantro: HEVC: Allows 10-bit bitstream</title>
<updated>2022-09-24T07:00:27Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@collabora.com</email>
</author>
<published>2022-08-29T16:21:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d040a24b5aaede6049fe27f2ea29773ada16a9e3'/>
<id>urn:sha1:d040a24b5aaede6049fe27f2ea29773ada16a9e3</id>
<content type='text'>
Stop limiting HEVC support to 8-bits bitstreams also
accept 10-bits bitstreams.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@collabora.com&gt;
Reviewed-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>media: hantro: postproc: Configure output regs to support 10bit</title>
<updated>2022-09-24T07:00:00Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@collabora.com</email>
</author>
<published>2022-08-29T16:21:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5aa24d729999c3d80034b29fc48f9957ad61fce8'/>
<id>urn:sha1:5aa24d729999c3d80034b29fc48f9957ad61fce8</id>
<content type='text'>
Move output format setting in postproc and make sure that
8/10bit configuration is correctly set.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@collabora.com&gt;
Reviewed-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>media: hantro: HEVC: Fix chroma offset computation</title>
<updated>2022-09-24T06:59:05Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@collabora.com</email>
</author>
<published>2022-08-29T16:21:55Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f64853ad7f964b3bf7c1d63b27ca7ef972797a1c'/>
<id>urn:sha1:f64853ad7f964b3bf7c1d63b27ca7ef972797a1c</id>
<content type='text'>
The chroma offset depends of the bitstream depth.
Make sure that ctx-&gt;bit_depth is used to compute it.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@collabora.com&gt;
Reviewed-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>media: hantro: HEVC: Fix auxilary buffer size calculation</title>
<updated>2022-09-24T06:58:12Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@collabora.com</email>
</author>
<published>2022-08-29T16:21:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8a438580a09ecef78cd6c5825d628b4d5ae1c127'/>
<id>urn:sha1:8a438580a09ecef78cd6c5825d628b4d5ae1c127</id>
<content type='text'>
SAO and FILTER buffers size depend of the bit depth.
Make sure we have enough space for 10bit bitstreams.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@collabora.com&gt;
Reviewed-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>media: hantro: Store HEVC bit depth in context</title>
<updated>2022-09-24T06:57:32Z</updated>
<author>
<name>Benjamin Gaignard</name>
<email>benjamin.gaignard@collabora.com</email>
</author>
<published>2022-08-29T16:21:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4bec03301ecd81760c159402467dbb2cfd527684'/>
<id>urn:sha1:4bec03301ecd81760c159402467dbb2cfd527684</id>
<content type='text'>
Store HEVC bit depth in context.
Bit depth is equal to hevc sps bit_depth_luma_minus8 + 8.

Signed-off-by: Benjamin Gaignard &lt;benjamin.gaignard@collabora.com&gt;
Reviewed-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
<entry>
<title>media: destage Hantro VPU driver</title>
<updated>2022-08-31T08:23:50Z</updated>
<author>
<name>Ezequiel Garcia</name>
<email>ezequiel@vanguardiasur.com.ar</email>
</author>
<published>2022-07-18T21:41:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=fbb6c848dd89786fe24856ee6b5e773910ded29c'/>
<id>urn:sha1:fbb6c848dd89786fe24856ee6b5e773910ded29c</id>
<content type='text'>
The Hantro mainline driver has been used in production
since several years and was only kept as a staging driver
due the stateless CODEC controls.

Now that all the stateless CODEC controls have been moved
out of staging, graduate the driver as well.

Signed-off-by: Ezequiel Garcia &lt;ezequiel@vanguardiasur.com.ar&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@kernel.org&gt;
</content>
</entry>
</feed>
