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<title>linux-dev/drivers/mtd/nand/bbt.c, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/mtd/nand/bbt.c?h=linus%2Fmaster</id>
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<updated>2021-05-10T16:20:54Z</updated>
<entry>
<title>mtd: nand: bbt: Fix corner case in bad block table handling</title>
<updated>2021-05-10T16:20:54Z</updated>
<author>
<name>Doyle, Patrick</name>
<email>pdoyle@irobot.com</email>
</author>
<published>2021-04-06T01:47:08Z</published>
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<id>urn:sha1:fd0d8d85f7230052e638a56d1bfea170c488e6bc</id>
<content type='text'>
In the unlikely event that both blocks 10 and 11 are marked as bad (on a
32 bit machine), then the process of marking block 10 as bad stomps on
cached entry for block 11.  There are (of course) other examples.

Signed-off-by: Patrick Doyle &lt;pdoyle@irobot.com&gt;
Reviewed-by: Richard Weinberger &lt;richard@nod.at&gt;
Signed-off-by: Yoshio Furuyama &lt;ytc-mb-yfuruyama7@kioxia.com&gt;
[&lt;miquel.raynal@bootlin.com&gt;: Fixed the title]
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/774a92693f311e7de01e5935e720a179fb1b2468.1616635406.git.ytc-mb-yfuruyama7@kioxia.com
</content>
</entry>
<entry>
<title>mtd: nand: Fix memory allocation in nanddev_bbt_init()</title>
<updated>2018-11-28T14:41:50Z</updated>
<author>
<name>Frieder Schrempf</name>
<email>frieder.schrempf@kontron.de</email>
</author>
<published>2018-11-27T07:44:52Z</published>
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<id>urn:sha1:40b412897ccb4b98b2cfb2a0aaabed58dd9e2086</id>
<content type='text'>
Fix the size of the buffer allocated to store the in-memory BBT.
This bug was previously hidden by a different bug, that was fixed in
commit d098093ba06e ("mtd: nand: Fix nanddev_neraseblocks()").

Fixes: 9c3736a3de21 ("mtd: nand: Add core infrastructure to deal with NAND devices")
Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Frieder Schrempf &lt;frieder.schrempf@kontron.de&gt;
Acked-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Boris Brezillon &lt;boris.brezillon@bootlin.com&gt;
</content>
</entry>
<entry>
<title>mtd: nand: Add core infrastructure to deal with NAND devices</title>
<updated>2018-02-16T09:10:53Z</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@bootlin.com</email>
</author>
<published>2018-02-05T22:02:05Z</published>
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<id>urn:sha1:9c3736a3de21d916a6af0594418b85a112f4bef6</id>
<content type='text'>
Add an intermediate layer to abstract NAND device interface so that
some logic can be shared between SPI NANDs, parallel/raw NANDs,
OneNANDs, ...

Signed-off-by: Boris Brezillon &lt;boris.brezillon@bootlin.com&gt;
</content>
</entry>
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