<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/mtd/nand/raw/Makefile, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/mtd/nand/raw/Makefile?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/mtd/nand/raw/Makefile?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-04-27T16:12:35Z</updated>
<entry>
<title>mtd: nand: make mtk_ecc.c a separated module</title>
<updated>2022-04-27T16:12:35Z</updated>
<author>
<name>Chuanhong Guo</name>
<email>gch981213@gmail.com</email>
</author>
<published>2022-04-24T03:25:23Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4fd62f15afa0d0da4823f429a2fb4c3492a84edf'/>
<id>urn:sha1:4fd62f15afa0d0da4823f429a2fb4c3492a84edf</id>
<content type='text'>
this code will be used in mediatek snfi spi-mem controller with
pipelined ECC engine.

Signed-off-by: Chuanhong Guo &lt;gch981213@gmail.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20220424032527.673605-2-gch981213@gmail.com
</content>
</entry>
<entry>
<title>mtd: rawnand: renesas: Add new NAND controller driver</title>
<updated>2021-12-21T17:06:35Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2021-12-17T14:20:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d8701fe890ecbab239086e7053d62d0f08587d7c'/>
<id>urn:sha1:d8701fe890ecbab239086e7053d62d0f08587d7c</id>
<content type='text'>
Introduce Renesas NAND controller driver which currently supports the
following features on R-Car Gen3 and RZ/N1 SoCs:
- All ONFI timing modes
- Different configurations of its internal ECC controller
- On-die (not tested) and software ECC support
- Several chips (not tested)
- Subpage accesses
- DMA and PIO

This controller was originally provided by Evatronix before being bought
by Cadence.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Tested-by: Ralph Siemsen &lt;ralph.siemsen@linaro.org&gt;
Acked-by: Wolfram Sang &lt;wsa+renesas@sang-engineering.com&gt;
Link: https://lore.kernel.org/linux-mtd/20211217142033.353599-3-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: rawnand: pl353: Add support for the ARM PL353 SMC NAND controller</title>
<updated>2021-06-18T07:45:21Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2021-06-10T08:20:40Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=08d8c62164a322eb923034acacf25246b775593a'/>
<id>urn:sha1:08d8c62164a322eb923034acacf25246b775593a</id>
<content type='text'>
This hardware controller is embedded in XilinX Zynq-7000 SoCs and has
partial support for Hamming ECC correction.

This work is inspired from the original contributions of Punnaiah
Choudary Kalluri and Naga Sureshkumar Relli.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Tested-by: Michael Walle &lt;michael@walle.cc&gt; [on zynq-7000]
Link: https://lore.kernel.org/linux-mtd/20210610082040.2075611-19-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: rawnand: tango: Remove the driver</title>
<updated>2021-02-01T17:59:19Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2021-01-20T15:05:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=94d07f6a539db14ced8c0c2ae6ed4ab9623a24ab'/>
<id>urn:sha1:94d07f6a539db14ced8c0c2ae6ed4ab9623a24ab</id>
<content type='text'>
The tango platform is getting removed [1], so the driver is no
longer needed.

[1] https://lore.kernel.org/linux-arm-kernel/20210120124812.2800027-1-arnd@kernel.org/T/

Cc: Marc Gonzalez &lt;marc.w.gonzalez@free.fr&gt;
Cc: Mans Rullgard &lt;mans@mansr.com&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20210120150555.1610132-1-arnd@kernel.org
</content>
</entry>
<entry>
<title>mtd: rawnand: rockchip: NFC driver for RK3308, RK2928 and others</title>
<updated>2020-12-10T21:37:33Z</updated>
<author>
<name>Yifeng Zhao</name>
<email>yifeng.zhao@rock-chips.com</email>
</author>
<published>2020-12-10T00:21:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=058e0e847d54944c5dc9ec6d29727e1449feb131'/>
<id>urn:sha1:058e0e847d54944c5dc9ec6d29727e1449feb131</id>
<content type='text'>
This driver supports Rockchip NFC (NAND Flash Controller) found on RK3308,
RK2928, RKPX30, RV1108 and other SOCs. The driver has been tested using
8-bit NAND interface on the ARM based RK3308 platform.

Support Rockchip SoCs and NFC versions:
- PX30 and RK3326(NFCv900).
	ECC: 16/40/60/70 bits/1KB.
	CLOCK: ahb and nfc.
- RK3308 and RV1108(NFCv800).
	ECC: 16 bits/1KB.
	CLOCK: ahb and nfc.
- RK3036 and RK3128(NFCv622).
	ECC: 16/24/40/60 bits/1KB.
	CLOCK: ahb and nfc.
- RK3066, RK3188 and RK2928(NFCv600).
	ECC: 16/24/40/60 bits/1KB.
	CLOCK: ahb.

Supported features:
- Read full page data by DMA.
- Support HW ECC(one step is 1KB).
- Support 2 - 32K page size.
- Support 8 CS(depend on SoCs)

Limitations:
- No support for the ecc step size is 512.
- Untested on some SoCs.
- No support for subpages.
- No support for the builtin randomizer.
- The original bad block mask is not supported. It is recommended to use
  the BBT(bad block table).

Suggested-by: Johan Jonker &lt;jbx6244@gmail.com&gt;
Signed-off-by: Yifeng Zhao &lt;yifeng.zhao@rock-chips.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20201210002134.5686-3-yifeng.zhao@rock-chips.com
</content>
</entry>
<entry>
<title>mtd: rawnand: Add NAND controller support on Intel LGM SoC</title>
<updated>2020-12-10T21:37:32Z</updated>
<author>
<name>Ramuthevar Vadivel Murugan</name>
<email>vadivel.muruganx.ramuthevar@linux.intel.com</email>
</author>
<published>2020-11-10T01:23:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0b1039f016e8a37c779a4aee362cb2100ebb1cfd'/>
<id>urn:sha1:0b1039f016e8a37c779a4aee362cb2100ebb1cfd</id>
<content type='text'>
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.

DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the read/write
operation from/to device.

Signed-off-by: Ramuthevar Vadivel Murugan &lt;vadivel.muruganx.ramuthevar@linux.intel.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20201110012333.18647-3-vadivel.muruganx.ramuthevar@linux.intel.com
</content>
</entry>
<entry>
<title>mtd: nand: ecc-hamming: Move Hamming code to the generic NAND layer</title>
<updated>2020-12-10T21:37:29Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2020-09-29T23:01:15Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e5acf9c862974041f7b2f581d1a40ccd29769add'/>
<id>urn:sha1:e5acf9c862974041f7b2f581d1a40ccd29769add</id>
<content type='text'>
Hamming ECC code might be later re-used by the SPI NAND layer.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20200929230124.31491-12-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: nand: ecc-bch: Move BCH code to the generic NAND layer</title>
<updated>2020-11-30T08:27:32Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2020-09-29T23:01:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cdbe8df5e28e452c232c0c16b205edfd390d28e5'/>
<id>urn:sha1:cdbe8df5e28e452c232c0c16b205edfd390d28e5</id>
<content type='text'>
BCH ECC code might be later re-used by the SPI NAND layer.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20200929230124.31491-3-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: rawnand: arasan: Add new Arasan NAND controller</title>
<updated>2020-05-24T20:34:55Z</updated>
<author>
<name>Miquel Raynal</name>
<email>miquel.raynal@bootlin.com</email>
</author>
<published>2020-05-19T07:45:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=197b88fecc50ee3c7a22415db81eae0b9126f20e'/>
<id>urn:sha1:197b88fecc50ee3c7a22415db81eae0b9126f20e</id>
<content type='text'>
Add the Arasan NAND controller driver. This brings only NAND
controller support. The ECC engine being a bit subtle, hardware ECC
support will be added in a second time.

This work is based on contributions from Naga Sureshkumar Relli.

Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Reviewed-by: Boris Brezillon &lt;boris.brezillon@collabora.com&gt;
Link: https://lore.kernel.org/linux-mtd/20200519074549.23673-8-miquel.raynal@bootlin.com
</content>
</entry>
<entry>
<title>mtd: rawnand: Remove the cmx270 NAND controller driver</title>
<updated>2020-05-24T18:39:53Z</updated>
<author>
<name>Boris Brezillon</name>
<email>boris.brezillon@collabora.com</email>
</author>
<published>2020-05-18T16:33:00Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=767727b927aa48e429c6fa92d4b55cc235fffe95'/>
<id>urn:sha1:767727b927aa48e429c6fa92d4b55cc235fffe95</id>
<content type='text'>
The CM-X270 board has been removed, we can remove the custom NAND
driver as well.

Signed-off-by: Boris Brezillon &lt;boris.brezillon@collabora.com&gt;
Acked-by: Robert Jarzmik &lt;robert.jarzmik@free.fr&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Link: https://lore.kernel.org/linux-mtd/20200518163300.304732-1-boris.brezillon@collabora.com
</content>
</entry>
</feed>
