<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/net/ethernet/cadence, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/net/ethernet/cadence?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/net/ethernet/cadence?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-10-21T04:12:00Z</updated>
<entry>
<title>net: macb: Specify PHY PM management done by MAC</title>
<updated>2022-10-21T04:12:00Z</updated>
<author>
<name>Sergiu Moga</name>
<email>sergiu.moga@microchip.com</email>
</author>
<published>2022-10-19T12:09:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=15a9dbec631cd69dfbbfc4e2cbf90c9dd8432a8f'/>
<id>urn:sha1:15a9dbec631cd69dfbbfc4e2cbf90c9dd8432a8f</id>
<content type='text'>
The `macb_resume`/`macb_suspend` methods already call the
`phylink_start`/`phylink_stop` methods during their execution so
explicitly say that the PM of the PHY is done by MAC by using the
`mac_managed_pm` flag of the `struct phylink_config`.

This also fixes the warning message issued during resume:
WARNING: CPU: 0 PID: 237 at drivers/net/phy/phy_device.c:323 mdio_bus_phy_resume+0x144/0x148

Depends-on: 96de900ae78e ("net: phylink: add mac_managed_pm in phylink_config structure")
Fixes: 744d23c71af3 ("net: phy: Warn about incorrect mdio_bus_phy_resume() state")
Signed-off-by: Sergiu Moga &lt;sergiu.moga@microchip.com&gt;
Reviewed-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Link: https://lore.kernel.org/r/20221019120929.63098-1-sergiu.moga@microchip.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net</title>
<updated>2022-09-29T21:30:51Z</updated>
<author>
<name>Jakub Kicinski</name>
<email>kuba@kernel.org</email>
</author>
<published>2022-09-29T21:30:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=accc3b4a572bba903a801a393532272727f83f5b'/>
<id>urn:sha1:accc3b4a572bba903a801a393532272727f83f5b</id>
<content type='text'>
No conflicts.

Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: drop the weight argument from netif_napi_add</title>
<updated>2022-09-29T01:57:14Z</updated>
<author>
<name>Jakub Kicinski</name>
<email>kuba@kernel.org</email>
</author>
<published>2022-09-27T13:27:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b48b89f9c189d24eb5e2b4a0ac067da5a24ee86d'/>
<id>urn:sha1:b48b89f9c189d24eb5e2b4a0ac067da5a24ee86d</id>
<content type='text'>
We tell driver developers to always pass NAPI_POLL_WEIGHT
as the weight to netif_napi_add(). This may be confusing
to newcomers, drop the weight argument, those who really
need to tweak the weight can use netif_napi_add_weight().

Acked-by: Marc Kleine-Budde &lt;mkl@pengutronix.de&gt; # for CAN
Link: https://lore.kernel.org/r/20220927132753.750069-1-kuba@kernel.org
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>net: macb: Fix ZynqMP SGMII non-wakeup source resume failure</title>
<updated>2022-09-23T11:32:49Z</updated>
<author>
<name>Radhey Shyam Pandey</name>
<email>radhey.shyam.pandey@amd.com</email>
</author>
<published>2022-09-21T13:36:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f22bd29ba19a43e758b192429613e04aa7abb70d'/>
<id>urn:sha1:f22bd29ba19a43e758b192429613e04aa7abb70d</id>
<content type='text'>
When GEM is in SGMII mode and disabled as a wakeup source, the power
management controller can power down the entire full power domain(FPD)
if none of the FPD devices are in use.

Incase of FPD off, there are below ethernet link up issues on non-wakeup
suspend/resume. To fix it add phy_exit() in suspend and phy_init() in the
resume path which reinitializes PS GTR SGMII lanes.

$ echo +20 &gt; /sys/class/rtc/rtc0/wakealarm
$ echo mem &gt; /sys/power/state

After resume:

$ ifconfig eth0 up
xilinx-psgtr fd400000.phy: lane 0 (type 10, protocol 5): PLL lock timeout
phy phy-fd400000.phy.0: phy poweron failed --&gt; -110
xilinx-psgtr fd400000.phy: lane 0 (type 10, protocol 5): PLL lock timeout
SIOCSIFFLAGS: Connection timed out
phy phy-fd400000.phy.0: phy poweron failed --&gt; -110

Fixes: 8b73fa3ae02b ("net: macb: Added ZynqMP-specific initialization")
Signed-off-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@amd.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: macb: Add zynqmp SGMII dynamic configuration support</title>
<updated>2022-09-20T15:33:05Z</updated>
<author>
<name>Radhey Shyam Pandey</name>
<email>radhey.shyam.pandey@amd.com</email>
</author>
<published>2022-09-14T12:33:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=32cee7818111fa350e654b121b4eb6c9a3e580c5'/>
<id>urn:sha1:32cee7818111fa350e654b121b4eb6c9a3e580c5</id>
<content type='text'>
Add support for the dynamic configuration which takes care of
configuring the GEM secure space configuration registers
using EEMI APIs.
High level sequence is to:
- Check for the PM dynamic configuration support, if no error proceed with
  GEM dynamic configurations(next steps) otherwise skip the dynamic
  configuration.
- Configure GEM Fixed configurations.
- Configure GEM_CLK_CTRL (gemX_sgmii_mode).
- Trigger GEM reset.

Signed-off-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@amd.com&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Tested-by: Conor Dooley &lt;conor.dooley@microchip.com&gt; (for MPFS)
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/egtvedt/linux-avr32</title>
<updated>2022-08-04T22:20:39Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-08-04T22:20:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=25e6bed5a64836621e41bc9f9d97eb79f1bdfa1e'/>
<id>urn:sha1:25e6bed5a64836621e41bc9f9d97eb79f1bdfa1e</id>
<content type='text'>
Pull AVR32 updates from Hans-Christian Noren Egtvedt:
 "Mostly changes to documentation and comments"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/egtvedt/linux-avr32:
  video:backlight: remove reference to AVR32 architecture in ltv350qv
  video: remove support for non-existing atmel,at32ap-lcdc in atmel_lcdfb
  usb:udc: remove reference to AVR32 architecture in Atmel USBA Kconfig
  sound:spi: remove reference to AVR32 in Atmel AT73C213 DAC driver
  net: remove cdns,at32ap7000-macb device tree entry
  misc: update maintainer email address and description for atmel-ssc
  mfd: remove reference to AVR32 architecture in atmel-smc.c
  dma:dw: remove reference to AVR32 architecture in core.c
</content>
</entry>
<entry>
<title>net: remove cdns,at32ap7000-macb device tree entry</title>
<updated>2022-08-03T09:03:03Z</updated>
<author>
<name>Hans-Christian Noren Egtvedt</name>
<email>egtvedt@samfundet.no</email>
</author>
<published>2017-11-05T10:19:53Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8bfdfbb258913047b5d5384ec2a6b049af1bf437'/>
<id>urn:sha1:8bfdfbb258913047b5d5384ec2a6b049af1bf437</id>
<content type='text'>
The AVR32 architecture has been removed from the kernel in commit
26202873bb51fafdaa51be3e8de7aab9beb49f70, hence clean out the
cdns,at32ap7000-macb compatible entry in Cadence macb Ethernet driver.

AVR32 architecture never supported device tree, hence this code was not
used by anybody.

Updated documentation to match the default entry, no users of
cdns,at32ap7000-macb in the kernel tree.

Signed-off-by: Hans-Christian Noren Egtvedt &lt;egtvedt@samfundet.no&gt;
</content>
</entry>
<entry>
<title>net: cdns,macb: use correct xlnx prefix for Xilinx</title>
<updated>2022-07-28T11:08:53Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2022-07-26T07:08:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=623cd87006983935de6c2ad8e2d50e68f1b7d6e7'/>
<id>urn:sha1:623cd87006983935de6c2ad8e2d50e68f1b7d6e7</id>
<content type='text'>
Use correct vendor for Xilinx versions of Cadence MACB/GEM Ethernet
controller.  The Versal compatible was not released, so it can be
changed.  Zynq-7xxx and Ultrascale+ has to be kept in new and deprecated
form.

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Acked-by: Harini Katakam &lt;harini.katakam@amd.com&gt;
Link: https://lore.kernel.org/r/20220726070802.26579-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Paolo Abeni &lt;pabeni@redhat.com&gt;
</content>
</entry>
<entry>
<title>net: macb: Update tsu clk usage in runtime suspend/resume for Versal</title>
<updated>2022-07-25T11:29:54Z</updated>
<author>
<name>Harini Katakam</name>
<email>harini.katakam@xilinx.com</email>
</author>
<published>2022-07-22T11:03:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8a1c9753f1653f30e508547a971f6a7ed365a4fb'/>
<id>urn:sha1:8a1c9753f1653f30e508547a971f6a7ed365a4fb</id>
<content type='text'>
On Versal TSU clock cannot be disabled irrespective of whether PTP is
used. Hence introduce a new Versal config structure with a "need tsu"
caps flag and check the same in runtime_suspend/resume before cutting
off clocks.

More information on this for future reference:
This is an IP limitation on versions 1p11 and 1p12 when Qbv is enabled
(See designcfg1, bit 3). However it is better to rely on an SoC specific
check rather than the IP version because tsu clk property itself may not
represent actual HW tsu clock on some chip designs.

Signed-off-by: Harini Katakam &lt;harini.katakam@xilinx.com&gt;
Signed-off-by: Radhey Shyam Pandey &lt;radhey.shyam.pandey@xilinx.com&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>net: macb: Sort CAPS flags by bit positions</title>
<updated>2022-07-25T11:29:54Z</updated>
<author>
<name>Harini Katakam</name>
<email>harini.katakam@xilinx.com</email>
</author>
<published>2022-07-22T11:03:29Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=1d3ded642535cbb30b376dc3b321284762878e11'/>
<id>urn:sha1:1d3ded642535cbb30b376dc3b321284762878e11</id>
<content type='text'>
Sort capability flags by the bit position set.

Signed-off-by: Harini Katakam &lt;harini.katakam@xilinx.com&gt;
Reviewed-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
</feed>
