<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/ntb/hw/amd, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/ntb/hw/amd?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/ntb/hw/amd?h=master'/>
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<updated>2022-01-11T20:38:59Z</updated>
<entry>
<title>ntb_hw_amd: Add NTB PCI ID for new gen CPU</title>
<updated>2022-01-11T20:38:59Z</updated>
<author>
<name>Sanjay R Mehta</name>
<email>sanju.mehta@amd.com</email>
</author>
<published>2021-12-17T09:56:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0d5924ec4b89613910366c890305e46821a31f01'/>
<id>urn:sha1:0d5924ec4b89613910366c890305e46821a31f01</id>
<content type='text'>
Add NTB support for new generation of processor

Signed-off-by: Sanjay R Mehta &lt;sanju.mehta@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: switch from 'pci_' to 'dma_' API</title>
<updated>2021-09-05T22:08:14Z</updated>
<author>
<name>Christophe JAILLET</name>
<email>christophe.jaillet@wanadoo.fr</email>
</author>
<published>2021-08-22T14:04:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=38de3afffb7257176978dfa9b3ab67d0c29af95c'/>
<id>urn:sha1:38de3afffb7257176978dfa9b3ab67d0c29af95c</id>
<content type='text'>
The wrappers in include/linux/pci-dma-compat.h should go away.

The patch has been generated with the coccinelle script below.

It has been compile tested.

@@
@@
-    PCI_DMA_BIDIRECTIONAL
+    DMA_BIDIRECTIONAL

@@
@@
-    PCI_DMA_TODEVICE
+    DMA_TO_DEVICE

@@
@@
-    PCI_DMA_FROMDEVICE
+    DMA_FROM_DEVICE

@@
@@
-    PCI_DMA_NONE
+    DMA_NONE

@@
expression e1, e2, e3;
@@
-    pci_alloc_consistent(e1, e2, e3)
+    dma_alloc_coherent(&amp;e1-&gt;dev, e2, e3, GFP_)

@@
expression e1, e2, e3;
@@
-    pci_zalloc_consistent(e1, e2, e3)
+    dma_alloc_coherent(&amp;e1-&gt;dev, e2, e3, GFP_)

@@
expression e1, e2, e3, e4;
@@
-    pci_free_consistent(e1, e2, e3, e4)
+    dma_free_coherent(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_map_single(e1, e2, e3, e4)
+    dma_map_single(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_single(e1, e2, e3, e4)
+    dma_unmap_single(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4, e5;
@@
-    pci_map_page(e1, e2, e3, e4, e5)
+    dma_map_page(&amp;e1-&gt;dev, e2, e3, e4, e5)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_page(e1, e2, e3, e4)
+    dma_unmap_page(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_map_sg(e1, e2, e3, e4)
+    dma_map_sg(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_unmap_sg(e1, e2, e3, e4)
+    dma_unmap_sg(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_single_for_cpu(e1, e2, e3, e4)
+    dma_sync_single_for_cpu(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_single_for_device(e1, e2, e3, e4)
+    dma_sync_single_for_device(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_sg_for_cpu(e1, e2, e3, e4)
+    dma_sync_sg_for_cpu(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2, e3, e4;
@@
-    pci_dma_sync_sg_for_device(e1, e2, e3, e4)
+    dma_sync_sg_for_device(&amp;e1-&gt;dev, e2, e3, e4)

@@
expression e1, e2;
@@
-    pci_dma_mapping_error(e1, e2)
+    dma_mapping_error(&amp;e1-&gt;dev, e2)

@@
expression e1, e2;
@@
-    pci_set_dma_mask(e1, e2)
+    dma_set_mask(&amp;e1-&gt;dev, e2)

@@
expression e1, e2;
@@
-    pci_set_consistent_dma_mask(e1, e2)
+    dma_set_coherent_mask(&amp;e1-&gt;dev, e2)

Signed-off-by: Christophe JAILLET &lt;christophe.jaillet@wanadoo.fr&gt;
Acked-by: Serge Semin &lt;fancer.lancer@gmail.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: hw: amd: fix an issue about leak system resources</title>
<updated>2020-08-24T02:36:32Z</updated>
<author>
<name>Kaige Li</name>
<email>likaige@loongson.cn</email>
</author>
<published>2020-08-11T01:59:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=44a0a3c17919db1498cebb02ecf3cf4abc1ade7b'/>
<id>urn:sha1:44a0a3c17919db1498cebb02ecf3cf4abc1ade7b</id>
<content type='text'>
The related system resources were not released when pci_set_dma_mask(),
pci_set_consistent_dma_mask(), or pci_iomap() return error in the
amd_ntb_init_pci() function. Add pci_release_regions() to fix it.

Fixes: a1b3695820aa ("NTB: Add support for AMD PCI-Express Non-Transparent Bridge")
Signed-off-by: Kaige Li &lt;likaige@loongson.cn&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>ntb: hw: remove the code that sets the DMA mask</title>
<updated>2020-06-06T00:02:08Z</updated>
<author>
<name>Logan Gunthorpe</name>
<email>logang@deltatee.com</email>
</author>
<published>2020-05-06T04:21:48Z</published>
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<id>urn:sha1:f80fe8944e085a1065f4829a14af8394cad1c30f</id>
<content type='text'>
This patch removes the code that sets the DMA mask as it no longer
makes sense to do this.

Fixes: 7f46c8b3a552 ("NTB: ntb_tool: Add full multi-port NTB API support")
Signed-off-by: Logan Gunthorpe &lt;logang@deltatee.com&gt;
Tested-by: Alexander Fomichev &lt;fomichev.ru@gmail.com&gt;
Signed-off-by: Sanjay R Mehta &lt;sanju.mehta@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: add pci shutdown handler for AMD NTB</title>
<updated>2020-03-13T14:04:20Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2020-02-05T15:54:32Z</published>
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<id>urn:sha1:b350f0a3eb264962caefeb892af56c1b727ee03f</id>
<content type='text'>
The PCI shutdown handler is invoked in response
to system reboot or shutdown. A data transfer
might still be in flight when this happens. So
the very first action we take here is to send
a link down notification, so that any pending
data transfer is terminated. Rest of the actions
are same as that of PCI remove handler.

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: send DB event when driver is loaded or un-loaded</title>
<updated>2020-03-13T14:04:20Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2020-02-05T15:54:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ac10d4f6c2a8247de21655f4564b0e209c3c1dd4'/>
<id>urn:sha1:ac10d4f6c2a8247de21655f4564b0e209c3c1dd4</id>
<content type='text'>
When the driver on the local side is loaded, it sets
SIDE_READY bit in SIDE_INFO register. Likewise, when
it is un-loaded, it clears the bit.

Also just after being loaded, the driver polls for
peer SIDE_READY bit to be set. Since that bit is set
when the peer side driver has loaded, the polling on
local side breaks as soon as this condition is met.

But the situation is different when the driver is
un-loaded. Since the polling has already been stopped
as mentioned before, if the peer side driver gets
un-loaded, the driver on the local side is not notified
implicitly.

So, we improvise using existing doorbell mechanism.
We reserve the highest order bit of the DB register to
send a notification to peer when the driver on local
side is un-loaded. This also means that now we are one
short of 16 DB events and that is taken care of in the
valid DB mask.

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: remove redundant setting of DB valid mask</title>
<updated>2020-03-13T14:04:20Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2020-02-05T15:54:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=41dfc3f79650504f5047f20a4faacaff217ce37b'/>
<id>urn:sha1:41dfc3f79650504f5047f20a4faacaff217ce37b</id>
<content type='text'>
db_valid_mask is set at two places, once within
amd_init_ntb(), and again within amd_init_dev().
Since amd_init_ntb() is actually called from
amd_init_dev(), setting db_valid_mask from
former does not really make sense. So remove it.

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: return link up status correctly for PRI and SEC</title>
<updated>2020-03-13T14:04:20Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2020-02-05T15:54:29Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5f0856bebc6e02a57b36cd2146f056c71862f0b6'/>
<id>urn:sha1:5f0856bebc6e02a57b36cd2146f056c71862f0b6</id>
<content type='text'>
Since NTB connects two physically separate systems,
there can be scenarios where one system goes down
while the other one remains active. In case of NTB
primary, if the NTB secondary goes down, a Link-Down
event is received. For the NTB secondary, if the
NTB primary goes down, the PCIe hotplug mechanism
ensures that the driver on the secondary side is also
unloaded.

But there are other scenarios to consider as well,
when suppose the physical link remains active, but
the driver on primary or secondary side is loaded
or un-loaded.

When the driver is loaded, on either side, it sets
SIDE_READY bit(bit-1) of SIDE_INFO register. Similarly,
when the driver is un-loaded, it resets the same bit.

We consider the NTB link to be up and operational
only when the driver on both sides of link are loaded
and ready. But we also need to take account of
Link Up and Down events which signify the physical
link status. So amd_link_is_up() is modified to take
care of the above scenarios.

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: add helper functions to set and clear sideinfo</title>
<updated>2020-03-13T14:04:20Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2020-02-05T15:54:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ae5f4bdccf030d524f995dfc364ea6a96c22882c'/>
<id>urn:sha1:ae5f4bdccf030d524f995dfc364ea6a96c22882c</id>
<content type='text'>
We define two new helper functions to set and clear
sideinfo registers respectively. These functions
take an additional boolean parameter which signifies
whether we want to set/clear the sideinfo register
of the peer(true) or local host(false).

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
<entry>
<title>NTB: move ntb_ctrl handling to init and deinit</title>
<updated>2020-03-13T14:04:20Z</updated>
<author>
<name>Arindam Nath</name>
<email>arindam.nath@amd.com</email>
</author>
<published>2020-02-05T15:54:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=92abf4cb993ddce258acac32bd0068d1813a79d1'/>
<id>urn:sha1:92abf4cb993ddce258acac32bd0068d1813a79d1</id>
<content type='text'>
It does not really make sense to enable or disable
the bits of NTB_CTRL register only during enable
and disable link callbacks. They should be done
independent of these callbacks. The correct placement
for that is during the amd_init_side_info() and
amd_deinit_side_info() functions, which are invoked
during probe and remove respectively.

Signed-off-by: Arindam Nath &lt;arindam.nath@amd.com&gt;
Signed-off-by: Jon Mason &lt;jdmason@kudzu.us&gt;
</content>
</entry>
</feed>
