linux-dev/drivers/pci/controller/dwc/Makefile, branch linus/master

PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver

2021-10-11T20:34:02Z

Add driver for Qualcomm PCIe Endpoint controller based on the DesignWare core with added Qualcomm-specific wrapper around the core. The driver support is very basic such that it supports only enumeration, PCIe read/write, and MSI. There is no ASPM and PM support for now but these will be added later. The driver is capable of using the PERST# and WAKE# side-band GPIOs for operation and written on top of the DWC PCI framework. [bhelgaas: wrap a few long lines] Co-developed-by: Siddartha Mohanadoss [mani: restructured the driver and fixed several bugs for upstream] Link: https://lore.kernel.org/r/20210920065946.15090-3-manivannan.sadhasivam@linaro.org Signed-off-by: Siddartha Mohanadoss Signed-off-by: Manivannan Sadhasivam Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Rob Herring

Merge branch 'remotes/lorenzo/pci/keembay'

2021-09-02T19:56:48Z

- Add Intel Keem Bay PCIe controller driver and DT binding (Srikanth Thokala) * remotes/lorenzo/pci/keembay: PCI: keembay: Add support for Intel Keem Bay dt-bindings: PCI: Add Intel Keem Bay PCIe controller

Merge branch 'pci/visconti'

2021-09-02T19:56:46Z

- Add Toshiba Visconti PCIe host controller driver (Nobuhiro Iwamatsu) * pci/visconti: MAINTAINERS: Add entries for Toshiba Visconti PCIe controller PCI: visconti: Add Toshiba Visconti PCIe host controller driver

PCI: rockchip-dwc: Add Rockchip RK356X host controller driver

2021-08-31T19:58:20Z

Add a driver for the DesignWare-based PCIe controller found on RK356X. The existing pcie-rockchip-host driver is only used for the Rockchip-designed IP found on RK3399. Link: https://lore.kernel.org/r/20210625065511.1096935-1-xxm@rock-chips.com Tested-by: Peter Geis Signed-off-by: Simon Xue Signed-off-by: Shawn Lin Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Kever Yang Reviewed-by: Rob Herring

PCI: visconti: Add Toshiba Visconti PCIe host controller driver

2021-08-31T19:52:05Z

Add support for the PCIe RC controller on Toshiba Visconti ARM SoCs. This PCIe controller is based on the Synopsys DesignWare PCIe core. Link: https://lore.kernel.org/r/20210811083830.784065-3-nobuhiro1.iwamatsu@toshiba.co.jp Signed-off-by: Yuji Ishikawa Signed-off-by: Nobuhiro Iwamatsu Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Reviewed-by: Rob Herring

PCI: keembay: Add support for Intel Keem Bay

2021-08-20T12:47:05Z

Add driver for Intel Keem Bay SoC PCIe controller. This controller is based on DesignWare PCIe core. In Root Complex mode, only internal reference clock is possible for Keem Bay A0. For Keem Bay B0, external reference clock can be used and will be the default configuration. Currently, keembay_pcie_of_data structure has one member. It will be expanded later to handle this difference. Endpoint mode link initialization is handled by the boot firmware. Link: https://lore.kernel.org/r/20210805211010.29484-3-srikanth.thokala@intel.com Signed-off-by: Wan Ahmad Zainie Signed-off-by: Srikanth Thokala Signed-off-by: Lorenzo Pieralisi Reviewed-by: Krzysztof Wilczyński Reviewed-by: Rob Herring Acked-by: Andy Shevchenko

PCI: tegra194: Fix MCFG quirk build regressions

2021-06-18T15:32:34Z

7f100744749e ("PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata") caused a few build regressions: - 7f100744749e removed the Makefile rule for CONFIG_PCIE_TEGRA194, so pcie-tegra.c can no longer be built as a module. Restore that rule. - 7f100744749e added "#ifdef CONFIG_PCIE_TEGRA194" around the native driver, but that's only set when the driver is built-in (for a module, CONFIG_PCIE_TEGRA194_MODULE is defined). The ACPI quirk is completely independent of the rest of the native driver, so move the quirk to its own file and remove the #ifdef in the native driver. - 7f100744749e added symbols that are always defined but used only when CONFIG_PCIEASPM, which causes warnings when CONFIG_PCIEASPM is not set: drivers/pci/controller/dwc/pcie-tegra194.c:259:18: warning: ‘event_cntr_data_offset’ defined but not used [-Wunused-const-variable=] drivers/pci/controller/dwc/pcie-tegra194.c:250:18: warning: ‘event_cntr_ctrl_offset’ defined but not used [-Wunused-const-variable=] drivers/pci/controller/dwc/pcie-tegra194.c:243:27: warning: ‘pcie_gen_freq’ defined but not used [-Wunused-const-variable=] Fixes: 7f100744749e ("PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata") Link: https://lore.kernel.org/r/20210610064134.336781-1-jonathanh@nvidia.com Signed-off-by: Jon Hunter Signed-off-by: Bjorn Helgaas Reviewed-by: Thierry Reding

Merge branch 'pci/tegra'

2021-05-04T15:43:32Z

- Add MCFG quirks for Tegra194 ECAM errata (Vidya Sagar) * pci/tegra: PCI: tegra: Add Tegra194 MCFG quirks for ECAM errata

Merge branch 'remotes/lorenzo/pci/risc-v'

2021-05-04T15:43:28Z

- sifive: Add pcie_aux clock to prci driver (Greentime Hu) - sifive: Use reset-simple in prci driver for PCIe (Greentime Hu) - Add SiFive FU740 PCIe host controller driver and DT binding (Paul Walmsley, Greentime Hu) * remotes/lorenzo/pci/risc-v: riscv: dts: Add PCIe support for the SiFive FU740-C000 SoC PCI: fu740: Add SiFive FU740 PCIe host controller driver dt-bindings: PCI: Add SiFive FU740 PCIe host controller MAINTAINERS: Add maintainers for SiFive FU740 PCIe driver clk: sifive: Use reset-simple in prci driver for PCIe driver clk: sifive: Add pcie_aux clock in prci driver for PCIe driver

PCI: fu740: Add SiFive FU740 PCIe host controller driver

2021-05-04T13:58:22Z

Add driver for the SiFive FU740 PCIe host controller. This controller is based on the DesignWare PCIe core. Co-developed-by: Henry Styles Co-developed-by: Erik Danie Co-developed-by: Greentime Hu Link: https://lore.kernel.org/r/20210504105940.100004-6-greentime.hu@sifive.com Signed-off-by: Paul Walmsley Signed-off-by: Henry Styles Signed-off-by: Erik Danie Signed-off-by: Greentime Hu Signed-off-by: Lorenzo Pieralisi