<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/pci/host/Kconfig, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/pci/host/Kconfig?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/pci/host/Kconfig?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2018-06-08T12:50:11Z</updated>
<entry>
<title>PCI: Collect all native drivers under drivers/pci/controller/</title>
<updated>2018-06-08T12:50:11Z</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2018-05-31T01:12:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=6e0832fa432ec99c94caee733c8f5851cf85560b'/>
<id>urn:sha1:6e0832fa432ec99c94caee733c8f5851cf85560b</id>
<content type='text'>
Native PCI drivers for root complex devices were originally all in
drivers/pci/host/.  Some of these devices can also be operated in endpoint
mode.  Drivers for endpoint mode didn't seem to fit in the "host"
directory, so we put both the root complex and endpoint drivers in
per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc.

These per-device directories contain trivial Kconfig and Makefiles and
clutter drivers/pci/.  Make a new drivers/pci/controllers/ directory and
collect all the device-specific drivers there.

No functional change intended.

Link: https://lkml.kernel.org/r/1520304202-232891-1-git-send-email-shawn.lin@rock-chips.com
Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>Merge branch 'pci/kconfig'</title>
<updated>2018-06-06T21:10:49Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-06-06T21:10:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0ecda3a087462eb89c1d9227deea998d8cd014e8'/>
<id>urn:sha1:0ecda3a087462eb89c1d9227deea998d8cd014e8</id>
<content type='text'>
  - remove unnecessary host controller CONFIG_PCIEPORTBUS Kconfig
    selections (Bjorn Helgaas)

* pci/kconfig:
  PCI: Remove host driver Kconfig selection of CONFIG_PCIEPORTBUS

# Conflicts:
#	drivers/pci/dwc/Kconfig
#	drivers/pci/host/Kconfig
</content>
</entry>
<entry>
<title>Merge branch 'lorenzo/pci/rockchip'</title>
<updated>2018-06-06T21:10:43Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-06-06T21:10:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e52d38f4abf49f8b63a6ad0ce21e5f495c15897f'/>
<id>urn:sha1:e52d38f4abf49f8b63a6ad0ce21e5f495c15897f</id>
<content type='text'>
  - update arm64 defconfig for Rockchip (Shawn Lin)

  - refactor Rockchip code to facilitate both root port and endpoint mode
    (Shawn Lin)

  - add Rockchip endpoint mode driver (Shawn Lin)

* lorenzo/pci/rockchip:
  arm64: defconfig: update config for Rockchip PCIe
  dt-bindings: PCI: rockchip: Add DT bindings for Rockchip PCIe EP driver
  PCI: rockchip: Add EP driver for Rockchip PCIe controller
  dt-bindings: PCI: rockchip: Rename rockchip-pcie.txt to rockchip-pcie-host.txt
  PCI: rockchip: Split out common function to init controller
  PCI: rockchip: Split out rockchip_pcie_parse_dt() to parse DT
  PCI: rockchip: Separate common code from RC driver

# Conflicts:
#	drivers/pci/host/pcie-rockchip.c
</content>
</entry>
<entry>
<title>Merge branch 'lorenzo/pci/mediatek'</title>
<updated>2018-06-06T21:10:37Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-06-06T21:10:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cc64520f970a0b9a2d94c815d9bf5fd5c88f213d'/>
<id>urn:sha1:cc64520f970a0b9a2d94c815d9bf5fd5c88f213d</id>
<content type='text'>
  - implement Mediatek chained IRQ handling (Honghui Zhang)

  - fix vendor ID &amp; class type for Mediatek MT7622 (Honghui Zhang)

* lorenzo/pci/mediatek:
  PCI: mediatek: Implement chained IRQ handling setup
  PCI: mediatek: Set up vendor ID and class type for MT7622

# Conflicts:
#	drivers/pci/host/Kconfig
</content>
</entry>
<entry>
<title>Merge branch 'lorenzo/pci/host/misc'</title>
<updated>2018-06-06T21:10:33Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-06-06T21:10:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5db844eee501224f29bd67d6fea1ad4e3dd6cdde'/>
<id>urn:sha1:5db844eee501224f29bd67d6fea1ad4e3dd6cdde</id>
<content type='text'>
  - update Layerscape maintainer email addresses (Minghuan Lian)

  - add COMPILE_TEST to improve build test coverage (Rob Herring)

* lorenzo/pci/host/misc:
  MAINTAINERS: Update Layerscape PCIe driver maintainers list
  PCI: Improve host drivers compile test coverage

# Conflicts:
#	drivers/pci/dwc/Kconfig
</content>
</entry>
<entry>
<title>PCI: Enable PCI_DOMAINS along with generic PCI host controller</title>
<updated>2018-05-30T16:35:30Z</updated>
<author>
<name>Jan Kiszka</name>
<email>jan.kiszka@siemens.com</email>
</author>
<published>2018-05-15T09:07:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=37bd62d224c8244bccdb1a5bd7833a48c9ba8a66'/>
<id>urn:sha1:37bd62d224c8244bccdb1a5bd7833a48c9ba8a66</id>
<content type='text'>
The generic PCI host controller is often instantiated by hypervisors, and
they may add several of them or add them in addition to a physical host
controller like the Jailhouse hypervisor is doing.  Therefore, allow for
multiple domains so that we can handle them all.

Signed-off-by: Jan Kiszka &lt;jan.kiszka@siemens.com&gt;
Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: mediatek: Implement chained IRQ handling setup</title>
<updated>2018-05-21T13:43:45Z</updated>
<author>
<name>Honghui Zhang</name>
<email>honghui.zhang@mediatek.com</email>
</author>
<published>2018-05-04T05:47:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=42fe2f91b4ebc07c815fb334ea1262e6dc23bf77'/>
<id>urn:sha1:42fe2f91b4ebc07c815fb334ea1262e6dc23bf77</id>
<content type='text'>
Implement irq_chip based solution for IRQs management in order to
comply with IRQ framework.

Signed-off-by: Honghui Zhang &lt;honghui.zhang@mediatek.com&gt;
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Acked-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Reviewed-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: Remove host driver Kconfig selection of CONFIG_PCIEPORTBUS</title>
<updated>2018-05-18T20:08:36Z</updated>
<author>
<name>Bjorn Helgaas</name>
<email>bhelgaas@google.com</email>
</author>
<published>2018-05-18T20:08:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f3fdfc4ac3a26865e84627a7fe08a906081e5abc'/>
<id>urn:sha1:f3fdfc4ac3a26865e84627a7fe08a906081e5abc</id>
<content type='text'>
Host bridge drivers do not use the portdrv interfaces (struct pcie_device,
struct pcie_port_service_driver, pcie_port_service_register(), etc), and
they should not select CONFIG_PCIEPORTBUS.

If users need the portdrv services, they can select CONFIG_PCIEPORTBUS just
like all other PCI users.

Signed-off-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;</content>
</entry>
<entry>
<title>PCI: rockchip: Add EP driver for Rockchip PCIe controller</title>
<updated>2018-05-11T09:36:02Z</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2018-05-09T01:12:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cf590b07839133146842d2d3d9a68f804c2edc4b'/>
<id>urn:sha1:cf590b07839133146842d2d3d9a68f804c2edc4b</id>
<content type='text'>
Add support for the Rockchip PCIe controller in endpoint mode;
it currently supports up to 32 regions with each region spanning
at least 1MB as per TRM.

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
[lorenzo.pieralisi@arm.com: updated commit log]
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
</content>
</entry>
<entry>
<title>PCI: rockchip: Separate common code from RC driver</title>
<updated>2018-05-10T11:01:49Z</updated>
<author>
<name>Shawn Lin</name>
<email>shawn.lin@rock-chips.com</email>
</author>
<published>2018-05-09T01:11:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=956cd99b35a8fb9f7564702e7fd263c27b0a8f24'/>
<id>urn:sha1:956cd99b35a8fb9f7564702e7fd263c27b0a8f24</id>
<content type='text'>
In preparation for introducing EP driver for Rockchip PCIe controller,
rename the RC driver from pcie-rockchip.c to pcie-rockchip-host.c, and
only leave some common functions in pcie-rockchip.c in order to be
reused for both of RC driver and EP driver.

Signed-off-by: Shawn Lin &lt;shawn.lin@rock-chips.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Tested-by: Jeffy Chen &lt;jeffy.chen@rock-chips.com&gt;
</content>
</entry>
</feed>
