linux-dev/drivers/phy/cadence, branch master

phy: cadence-torrent: Remove unused `regmap` field from state struct

2022-07-08T05:10:43Z

The driver state struct for the sierra PHY driver has a field named `regmap` that is never referenced. Remove it since it is unused. Not that there are separate fields of type `struct regmap` for the individual sections of the device's register map. These other regmaps are used and not affected by the patch. Signed-off-by: Lars-Peter Clausen Link: https://lore.kernel.org/r/20220707071722.44201-2-lars@metafoo.de Signed-off-by: Vinod Koul

phy: cadence: Sierra: Remove unused `regmap` field from state struct

2022-07-08T05:10:43Z

phy: cdns-dphy: Add support for DPHY TX on J721e

2022-07-05T06:53:41Z

Add support new compatible for dphy-tx on j721e and implement dphy ops required. Signed-off-by: Rahul T R Reviewed-by: Pratyush Yadav Link: https://lore.kernel.org/r/20220623125433.18467-4-r-ravikumar@ti.com Signed-off-by: Vinod Koul

phy: cdns-dphy: Add band config for dphy tx

2022-07-05T06:53:41Z

Add support for band ctrl config for dphy tx. Signed-off-by: Rahul T R Reviewed-by: Pratyush Yadav Link: https://lore.kernel.org/r/20220623125433.18467-3-r-ravikumar@ti.com Signed-off-by: Vinod Koul

phy: cadence: Sierra: Add TI J721E specific PCIe multilink lane configuration

2022-04-13T09:56:54Z

This patch adds workaround for TI J721E errata i2183 (https://www.ti.com/lit/er/sprz455a/sprz455a.pdf). PCIe fails to link up if SERDES lanes not used by PCIe are assigned to another protocol. For example, link training fails if lanes 2 and 3 are assigned to another protocol while lanes 0 and 1 are used for PCIe to form a two lane link. This failure is due to an incorrect tie-off on an internal status signal indicating electrical idle. Status signals going from SERDES to PCIe Controller are tied-off when a lane is not assigned to PCIe. Signal indicating electrical idle is incorrectly tied-off to a state that indicates non-idle. As a result, PCIe sees unused lanes to be out of electrical idle and this causes LTSSM to exit Detect.Quiet state without waiting for 12ms timeout to occur. If a receiver is not detected on the first receiver detection attempt in Detect.Active state, LTSSM goes back to Detect.Quiet and again moves forward to Detect.Active state without waiting for 12ms as required by PCIe base specification. Since wait time in Detect.Quiet is skipped, multiple receiver detect operations are performed back-to-back without allowing time for capacitance on the transmit lines to discharge. This causes subsequent receiver detection to always fail even if a receiver gets connected eventually. The workaround only works for 1-lane PCIe configuration. This workaround involves enabling receiver detect override by setting TX_RCVDET_OVRD_PREG_j register of the lane running PCIe to 0x2. This causes SERDES to indicate successful receiver detect when LTSSM is in Detect.Active state, whether a receiver is actually present or not. If the receiver is present, LTSSM proceeds to link up as expected. However if receiver is not present, LTSSM will time out in Polling.Configuration substate since the expected training sequence packets will not be received. Signed-off-by: Swapnil Jakhade Link: https://lore.kernel.org/r/20220303055026.24899-1-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence: Add Cadence D-PHY Rx driver

2022-03-02T14:24:42Z

The Cadence D-PHY can be configured in Tx (DSI) mode or Rx (CSI) mode. Both modes have a different programming sequence and share little among them. In addition, a PHY configured in Tx mode cannot be used in Rx mode and vice versa. For this reason, create a separate driver for the Rx mode to make it easier to read and maintain. Signed-off-by: Pratyush Yadav Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20220301111621.2992275-2-p.yadav@ti.com Signed-off-by: Vinod Koul

phy/cadence: Use of_device_get_match_data()

2022-02-25T08:28:12Z

Use of_device_get_match_data() instead of open-coding it. Reported-by: Zeal Robot Signed-off-by: Minghao Chi (CGEL ZTE) Link: https://lore.kernel.org/r/20220214020626.1714696-1-chi.minghao@zte.com.cn Signed-off-by: Vinod Koul

phy: cadence: Sierra: Add support for skipping configuration

2022-02-07T04:57:43Z

In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: Aswath Govindraju Reviewed-by: Dan Carpenter Link: https://lore.kernel.org/r/20220128072642.29188-1-a-govindraju@ti.com Signed-off-by: Vinod Koul

phy: cadence: Sierra: fix error handling bugs in probe()

2022-01-24T04:05:31Z

There are two bugs in the error handling: 1: If devm_of_phy_provider_register() fails then there was no cleanup. 2: The error handling called of_node_put(child) improperly leading to a use after free. We are only holding the reference inside the loop so the last two gotos after the loop lead to a use after free bug. Fix this by cleaning up the partial allocations (or partial iterations) in the loop before doing the goto. Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Fixes: 44d30d622821 ("phy: cadence: Add driver for Sierra PHY") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20220115115146.GC7552@kili Signed-off-by: Vinod Koul

phy: cadence: Sierra: Add support for derived reference clock output

2021-12-27T11:05:09Z

Sierra has derived differential reference clock output which is sourced after the spread spectrum generation has been added. Add support to drive derived reference clock out of serdes. Model this derived clock as a "clock" so that platforms using this can enable it. Sierra Main LC VCO PLL divider 1 clock is programmed to output 100MHz clock output. Signed-off-by: Swapnil Jakhade Reviewed-by: Aswath Govindraju Link: https://lore.kernel.org/r/20211223060137.9252-16-sjakhade@cadence.com Signed-off-by: Vinod Koul