linux-dev/drivers/phy/st, branch linus/master

phy: stm32: fix a refcount leak in stm32_usbphyc_pll_enable()

2022-01-27T05:34:40Z

This error path needs to decrement "usbphyc->n_pll_cons.counter" before returning. Fixes: 5b1af71280ab ("phy: stm32: rework PLL Lock detection") Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20220112111724.GB3019@kili Signed-off-by: Vinod Koul

Merge tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy into char-misc-next

2021-12-30T13:02:16Z

Vinod writes: phy-for-5.17 - New support: - Qualcomm eDP PHY driver - Qualcomm SM8450 UFS, USB2, USB3, PCIe0 and PCIe1 phy support - Lan966x ethernet serdes PHY driver - Support for uniphier NXI & Pro4 SoC - Qualcomm SM6350 USB2 support - Amlogic Meson8 HDMI TX PHY driver - Rockchip rk3568 usb2 support - Intel Thunder Bay eMMC PHY driver - Freescale IMX8 PCIe phy driver - Updates: - Cadence Sierra driver updates for multilink configurations - Bcm usb2 updates for Phy reg space * tag 'phy-for-5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (72 commits) phy: cadence: Sierra: Add support for derived reference clock output dt-bindings: phy: cadence-sierra: Add clock ID for derived reference clock phy: cadence: Sierra: Add PCIe + QSGMII PHY multilink configuration phy: cadence: Sierra: Add support for PHY multilink configurations phy: cadence: Sierra: Fix to get correct parent for mux clocks phy: cadence: Sierra: Update single link PCIe register configuration phy: cadence: Sierra: Check PIPE mode PHY status to be ready for operation phy: cadence: Sierra: Check cmn_ready assertion during PHY power on phy: cadence: Sierra: Add PHY PCS common register configurations phy: cadence: Sierra: Rename some regmap variables to be in sync with Sierra documentation phy: cadence: Sierra: Add support to get SSC type from device tree dt-bindings: phy: cadence-sierra: Add binding to specify SSC mode dt-bindings: phy: cadence-torrent: Rename SSC macros to use generic names phy: cadence: Sierra: Prepare driver to add support for multilink configurations phy: cadence: Sierra: Use of_device_get_match_data() to get driver data phy: mediatek: Fix missing check in mtk_mipi_tx_probe phy: uniphier-usb3ss: fix unintended writing zeros to PHY register phy: phy-mtk-tphy: use new io helpers to access register phy: phy-mtk-xsphy: use new io helpers to access register phy: mediatek: add helpers to update bits of registers ...

phy: stm32: adopt dev_err_probe for regulators

2021-11-26T05:56:51Z

Change stm32-usbphyc driver to use dev_err_probe(), to benefit of devices_deferred debugfs in case of probe deferral. Signed-off-by: Fabrice Gasnier Reviewed-by: Amelie Delaunay Link: https://lore.kernel.org/r/1635172265-26219-1-git-send-email-fabrice.gasnier@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: fix st,slow-hs-slew-rate with st,decrease-hs-slew-rate

2021-11-16T09:58:51Z

st,decrease-hs-slew-rate is described in phy-stm32-usbphyc.yaml. Then fix the property name in driver. Fixes: 2f5e9f815a2f ("phy: stm32: add phy tuning support") Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20211026154817.198937-1-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: add phy tuning support

2021-10-26T11:06:22Z

It can be necessary to adjust the phys settings to compensate parasitics. This patch adds support of new optional properties to configure the tune interface of the phys of stm32-usbphyc. Properties are optional, that's why each property is skipped if not found (-EINVAL). Phy tuning is restored on resume because if deep low power state is achieved, phy tuning configuration is reset. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20211015161427.220784-4-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: restore utmi switch on resume

2021-10-26T11:06:22Z

UTMI switch value can be lost during suspend/resume, depending on the power state reached. This patch adds resume function to usbphyc, to reconfigure utmi switch after suspend. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20211015161427.220784-2-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy/drivers/stm32: use HZ macros

2021-09-08T18:50:26Z

HZ unit conversion macros are available in units.h, use them and remove the duplicate definition. Link: https://lkml.kernel.org/r/20210816114732.1834145-11-daniel.lezcano@linaro.org Signed-off-by: Daniel Lezcano Reviewed-by: Andy Shevchenko Cc: Chanwoo Choi Cc: Christian Eggers Cc: Guenter Roeck Cc: Jonathan Cameron Cc: Jonathan Cameron Cc: Kyungmin Park Cc: Lars-Peter Clausen Cc: Lukasz Luba Cc: Maxime Coquelin Cc: Miquel Raynal Cc: MyungJoo Ham Cc: Peter Meerwald Cc: "Rafael J. Wysocki" Cc: Zhang Rui Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds

phy: stm32: manage optional vbus regulator on phy_power_on/off

2021-05-31T08:38:58Z

This patch adds support for optional vbus regulator. It is managed on phy_power_on/off calls and may be needed for host mode. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210517120821.26466-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: register usbphyc as clock provider of ck_usbo_48m clock

2021-03-15T09:55:29Z

ck_usbo_48m is generated by usbphyc PLL and used by OTG controller for Full-Speed use cases with dedicated Full-Speed transceiver. ck_usbo_48m is available as soon as the PLL is enabled. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210208114659.15269-3-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul

phy: stm32: rework PLL Lock detection

2021-01-13T15:10:21Z

USBPHYC has a register per phy to control and monitor the debug interface of the HS PHY through a digital debug access. With this register, it is possible to know if PLL Lock input to phy is high. That means the PLL is ready for HS operation. Instead of using an hard-coded delay after PLL enable and PLL disable, use this bit to ensure good operating of the HS PHY. Also use an atomic counter (n_pll_cons) to count the actual number of PLL consumers and get rid of stm32_usbphyc_has_one_phy_active. The boolean active in the usbphyc_phy structure is kept, because we need to know in remove if a phy_exit is required to properly disable the PLL. Signed-off-by: Amelie Delaunay Link: https://lore.kernel.org/r/20210105090525.23164-7-amelie.delaunay@foss.st.com Signed-off-by: Vinod Koul