linux-dev/drivers/phy/ti, branch master

phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe()

2022-09-24T06:29:37Z

These two error paths need to call of_node_put(child_node) before returning. Fixes: edd473d4293a ("phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g") Fixes: 7ae14cf581f2 ("phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver") Signed-off-by: Dan Carpenter Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/YyxFI8aW23IC/21U@kili Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: stop name conflict if multiple serdes are initialized

2022-09-20T06:46:52Z

When multiple serdes instances are initialized the first will succeed but additional will conflict over clocks names and probing fails. Signed-off-by: Matt Ranostay Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20220909200026.3422-1-mranostay@ti.com Signed-off-by: Vinod Koul

phy: ti: gmii-sel: Add support for CPSW5G GMII SEL in J7200

2022-09-13T17:40:26Z

Each of the CPSW5G ports in J7200 support additional modes like QSGMII. Add a new compatible for J7200 to support the additional modes. In TI's J7200, each of the CPSW5G ethernet interfaces can act as a QSGMII or QSGMII-SUB port. The QSGMII interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. To indicate the interface which will serve as the main QSGMII interface, add a property "ti,qsgmii-main-ports", whose value indicates the port number of the interface which shall serve as the main QSGMII interface. The rest of the interfaces are then assigned QSGMII-SUB mode by default. The property "ti,qsgmii-main-ports" is used to configure the CTRLMMR_ENETx_CTRL register. Depending on the device, it is possible for more than one QSGMII main port to exist. Thus, the property "ti,qsgmii-main-ports" is defined as an array of values in order to reuse the property for other devices. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20220912085650.83263-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate

2022-08-30T05:12:58Z

For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g

2022-08-30T05:12:58Z

j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-7-rogerq@kernel.org Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver

2022-08-30T05:12:57Z

Changes the wiz_p_mac_div_sel() and wiz_mode_select() to configure serdes for USXGMII. Adds the support to configure mac_src_sel, refclk_sel and rxfclk_sel in the LANECTL register and configures the serdes for usxgmii. [rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code. Signed-off-by: Tanmay Patil Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-4-rogerq@kernel.org Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200

2022-08-30T05:12:57Z

Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli Signed-off-by: Vignesh Raghavendra Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-2-rogerq@kernel.org Signed-off-by: Vinod Koul

Merge tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx

2022-08-04T19:12:54Z

Pull SPDX updates from Greg KH: "Here is the set of SPDX comment updates for 6.0-rc1. Nothing huge here, just a number of updated SPDX license tags and cleanups based on the review of a number of common patterns in GPLv2 boilerplate text. Also included in here are a few other minor updates, two USB files, and one Documentation file update to get the SPDX lines correct. All of these have been in the linux-next tree for a very long time" * tag 'spdx-6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx: (28 commits) Documentation: samsung-s3c24xx: Add blank line after SPDX directive x86/crypto: Remove stray comment terminator treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_406.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_398.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_391.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_390.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_385.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_320.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_319.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_318.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_298.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_292.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_179.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 2) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_168.RULE (part 1) treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_160.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_152.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_149.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_147.RULE treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_133.RULE ...

phy: ti: tusb1210: Don't check for write errors when powering on

2022-07-05T05:27:32Z

On some platforms, like Intel Merrifield, the writing values during power on may timeout: tusb1210 dwc3.0.auto.ulpi: error -110 writing val 0x41 to reg 0x80 phy phy-dwc3.0.auto.ulpi.0: phy poweron failed --> -110 dwc3 dwc3.0.auto: error -ETIMEDOUT: failed to initialize core dwc3: probe of dwc3.0.auto failed with error -110 which effectively fails the probe of the USB controller. Drop the check as it was before the culprit commit (see Fixes tag). Fixes: 09a3512681b3 ("phy: ti: tusb1210: Improve ulpi_read()/_write() error checking") Signed-off-by: Andy Shevchenko Acked-by: Hans de Goede Tested-by: Ferry Toth Link: https://lore.kernel.org/r/20220613160848.82746-1-andriy.shevchenko@linux.intel.com Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: use OF data for device specific data

2022-06-17T00:33:43Z

Move device specific data into OF data structure so it is easier to maintain and we can get rid of if statements. Signed-off-by: Roger Quadros Reviewed-by: Matt Ranostay Link: https://lore.kernel.org/r/20220526064121.27625-1-rogerq@kernel.org Signed-off-by: Vinod Koul