<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/pinctrl/qcom/Kconfig, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/pinctrl/qcom/Kconfig?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/pinctrl/qcom/Kconfig?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-04-22T22:04:43Z</updated>
<entry>
<title>pinctrl: qcom: Add SC7280 lpass pin configuration</title>
<updated>2022-04-22T22:04:43Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=120a5f2e5430ca3908d8b7639105d95f12ac135c'/>
<id>urn:sha1:120a5f2e5430ca3908d8b7639105d95f12ac135c</id>
<content type='text'>
Add pin control support for SC7280 LPASS LPI.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-7-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Extract chip specific LPASS LPI code</title>
<updated>2022-04-22T22:04:43Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9ce49018c6928263d41b783c9e4928c6af05db43'/>
<id>urn:sha1:9ce49018c6928263d41b783c9e4928c6af05db43</id>
<content type='text'>
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Update lpi pin group custiom functions with framework generic functions</title>
<updated>2022-04-22T22:04:43Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=be73368d535614b351c13a10680b4cdd06db2417'/>
<id>urn:sha1:be73368d535614b351c13a10680b4cdd06db2417</id>
<content type='text'>
Update custom pin group structure members with framework generic
group_desc structure and replace the driver's custom pinctrl_ops
with framework provided generic pin control group functions to avoid
redundant code written in lpass lpi driver.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-5-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Introduce sc8280xp TLMM driver</title>
<updated>2022-03-15T01:03:46Z</updated>
<author>
<name>Bjorn Andersson</name>
<email>bjorn.andersson@linaro.org</email>
</author>
<published>2022-03-08T22:11:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c0e4c71a9e7ceea8f14e0b875fcc23266caf05e6'/>
<id>urn:sha1:c0e4c71a9e7ceea8f14e0b875fcc23266caf05e6</id>
<content type='text'>
The SC8280XP comes, like all other Qualcomm platforms, with a TLMM
block, so add a driver for it.

Signed-off-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220308221132.1423218-2-bjorn.andersson@linaro.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add SM8450 pinctrl driver</title>
<updated>2021-12-09T02:01:30Z</updated>
<author>
<name>Vinod Koul</name>
<email>vkoul@kernel.org</email>
</author>
<published>2021-12-01T07:24:34Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4beb02f19c37e6fbe941d786119ed82ec0aca19a'/>
<id>urn:sha1:4beb02f19c37e6fbe941d786119ed82ec0aca19a</id>
<content type='text'>
This adds pincontrol driver for tlmm block found in SM8450 SoC

This patch is based on initial code downstream by
Elliot Berman &lt;eberman@codeaurora.org&gt;

Signed-off-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Tested-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20211201072434.3968768-3-vkoul@kernel.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'v5.16-rc2' into devel</title>
<updated>2021-11-26T23:54:16Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2021-11-26T23:54:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2448eab44034d9603c97ca17760a53d4d6e4b60c'/>
<id>urn:sha1:2448eab44034d9603c97ca17760a53d4d6e4b60c</id>
<content type='text'>
Linux 5.16-rc2 is needed because nonurgent fixes headed
for next are strongly textually dependent on a fix that
was applied for rc2.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add SDX65 pincontrol driver</title>
<updated>2021-11-21T22:48:27Z</updated>
<author>
<name>Vamsi Krishna Lanka</name>
<email>quic_vamslank@quicinc.com</email>
</author>
<published>2021-11-16T07:39:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=bdbf104f8ee6e9b32e9819a8d3b4d8a3f8f4f1f2'/>
<id>urn:sha1:bdbf104f8ee6e9b32e9819a8d3b4d8a3f8f4f1f2</id>
<content type='text'>
Add initial Qualcomm SDX65 pinctrl driver to support pin configuration
with pinctrl framework for SDX65 SoC.

Signed-off-by: Vamsi Krishna Lanka &lt;quic_vamslank@quicinc.com&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/13acb3cb36349487dee9745ab040d8f1344d2096.1637048107.git.quic_vamslank@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: fix unmet dependencies on GPIOLIB for GPIOLIB_IRQCHIP</title>
<updated>2021-11-16T01:19:14Z</updated>
<author>
<name>Julian Braha</name>
<email>julianbraha@gmail.com</email>
</author>
<published>2021-10-29T00:46:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=60430d4c4eddcdf8eac2bdbec9704f84a436eedf'/>
<id>urn:sha1:60430d4c4eddcdf8eac2bdbec9704f84a436eedf</id>
<content type='text'>
When PINCTRL_QCOM_SPMI_PMIC or PINCTRL_QCOM_SSBI_PMIC
is selected, and GPIOLIB is not selected, Kbuild
gives the following warnings:

WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP
  Depends on [n]: GPIOLIB [=n]
  Selected by [y]:
  - PINCTRL_QCOM_SPMI_PMIC [=y] &amp;&amp; PINCTRL [=y] &amp;&amp; (ARCH_QCOM [=n] || COMPILE_TEST [=y]) &amp;&amp; OF [=y] &amp;&amp; SPMI [=y]

WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP
  Depends on [n]: GPIOLIB [=n]
  Selected by [y]:
  - PINCTRL_QCOM_SSBI_PMIC [=y] &amp;&amp; PINCTRL [=y] &amp;&amp; (ARCH_QCOM [=n] || COMPILE_TEST [=y]) &amp;&amp; OF [=y]

This is because these config options enable GPIOLIB_IRQCHIP
without selecting or depending on GPIOLIB, despite
GPIOLIB_IRQCHIP depending on GPIOLIB.

These unmet dependency bugs were detected by Kismet,
a static analysis tool for Kconfig. Please advise if this
is not the appropriate solution.

Signed-off-by: Julian Braha &lt;julianbraha@gmail.com&gt;
Link: https://lore.kernel.org/r/20211029004610.35131-1-julianbraha@gmail.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2021-11-05T15:24:17Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-11-05T15:24:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5a1bcbd965341537c354e3682f939a7274ac3f5d'/>
<id>urn:sha1:5a1bcbd965341537c354e3682f939a7274ac3f5d</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "The most interesting aspect is that we now have initial support for
  the Apple pin controller as used in the M1 laptops and the iPhones
  which is a step forward for using Linux efficiently on this Apple
  silicon.

  Core changes:

   - Add infrastructure for per-parent interrupt data to support the
     Apple pin controller.

  New drivers:

   - New combined pin control and GPIO driver for the Apple SoC. This is
     used in all modern Apple silicon such as the M1 laptops but also in
     at least recent iPhone variants.

   - New subdriver for the Qualcomm SM6350

   - New subdriver for the Qualcomm QCM2290

   - New subdriver for the Qualcomm PM6350

   - New subdriver for the Uniphier NX1

   - New subdriver for the Samsung ExynosAutoV9

   - New subdriver for the Mediatek MT7986

   - New subdriver for the nVidia Tegra194

  Improvements:

   - Improve power management in the Mediatek driver.

   - Improvements to the Renesas internal consistency checker.

   - Convert the Rockchip pin control device tree bindings to YAML.

   - Finally convert the Qualcomm PMIC SSBI and SPMI MPP GPIO driver to
     use hierarchical interrupts.

   - Convert the Qualcomm PMIC MPP device tree bindings to YAML"

* tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (55 commits)
  pinctrl: add pinctrl/GPIO driver for Apple SoCs
  dt-bindings: pinctrl: Add apple,npins property to apple,pinctrl
  dt-bindings: pinctrl: add #interrupt-cells to apple,pinctrl
  gpio: Allow per-parent interrupt data
  pinctrl: tegra: Fix warnings and error
  pinctrl: intel: Kconfig: Add configuration menu to Intel pin control
  pinctrl: tegra: Use correct offset for pin group
  pinctrl: core: fix possible memory leak in pinctrl_enable()
  pinctrl: bcm2835: Allow building driver as a module
  pinctrl: equilibrium: Fix function addition in multiple groups
  pinctrl: tegra: Add pinmux support for Tegra194
  pinctrl: tegra: include lpdr pin properties
  pinctrl: mediatek: add support for MT7986 SoC
  dt-bindings: pinctrl: update bindings for MT7986 SoC
  pinctrl: microchip sgpio: use reset driver
  dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add reset binding
  dt-bindings: pinctrl: qcom,pmic-mpp: switch to #interrupt-cells
  pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip
  pinctrl: qcom: spmi-mpp: hardcode IRQ counts
  pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chip
  ...
</content>
</entry>
<entry>
<title>qcom_scm: hide Kconfig symbol</title>
<updated>2021-10-07T14:51:57Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2021-09-28T07:50:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=424953cf3c6657f1e67e1a2c5d6e3bb518ea4e9a'/>
<id>urn:sha1:424953cf3c6657f1e67e1a2c5d6e3bb518ea4e9a</id>
<content type='text'>
Now that SCM can be a loadable module, we have to add another
dependency to avoid link failures when ipa or adreno-gpu are
built-in:

aarch64-linux-ld: drivers/net/ipa/ipa_main.o: in function `ipa_probe':
ipa_main.c:(.text+0xfc4): undefined reference to `qcom_scm_is_available'

ld.lld: error: undefined symbol: qcom_scm_is_available
&gt;&gt;&gt; referenced by adreno_gpu.c
&gt;&gt;&gt;               gpu/drm/msm/adreno/adreno_gpu.o:(adreno_zap_shader_load) in archive drivers/built-in.a

This can happen when CONFIG_ARCH_QCOM is disabled and we don't select
QCOM_MDT_LOADER, but some other module selects QCOM_SCM. Ideally we'd
use a similar dependency here to what we have for QCOM_RPROC_COMMON,
but that causes dependency loops from other things selecting QCOM_SCM.

This appears to be an endless problem, so try something different this
time:

 - CONFIG_QCOM_SCM becomes a hidden symbol that nothing 'depends on'
   but that is simply selected by all of its users

 - All the stubs in include/linux/qcom_scm.h can go away

 - arm-smccc.h needs to provide a stub for __arm_smccc_smc() to
   allow compile-testing QCOM_SCM on all architectures.

 - To avoid a circular dependency chain involving RESET_CONTROLLER
   and PINCTRL_SUNXI, drop the 'select RESET_CONTROLLER' statement.
   According to my testing this still builds fine, and the QCOM
   platform selects this symbol already.

Acked-by: Kalle Valo &lt;kvalo@codeaurora.org&gt;
Acked-by: Alex Elder &lt;elder@linaro.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
</feed>
