linux-dev/drivers/pinctrl/qcom/Makefile, branch master

pinctrl: qcom: Add sc8280xp lpass lpi pinctrl driver

2022-08-25T12:32:04Z

Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SC8280XP. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220817113747.9111-3-srinivas.kandagatla@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver

2022-08-25T12:29:56Z

Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8450. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220817113833.9625-3-srinivas.kandagatla@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add SM6375 TLMM driver

2022-07-26T07:28:53Z

Add a driver to control the TLMM block on SM6375. This is an adapted version of msm-5.4's pinctrl-blair driver. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20220716192900.454653-2-konrad.dybcio@somainline.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add pinctrl driver for MSM8909

2022-07-11T08:26:52Z

Make it possible to control pins using the TLMM block in the MSM8909 SoC by adding the necessary definitions for GPIOs, groups and functions. The driver is originally taken from the msm-4.9 release [1] from Qualcomm, but cleaned up significantly with several fixes and clarifications. [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c Signed-off-by: Stephan Gerhold Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add SC7280 lpass pin configuration

2022-04-22T22:04:43Z

Add pin control support for SC7280 LPASS LPI. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1650285427-19752-7-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Extract chip specific LPASS LPI code

2022-04-22T22:04:43Z

Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver to allow reusing the common code in the addition of subsequent platforms. Signed-off-by: Srinivasa Rao Mandadapu Co-developed-by: Venkata Prasad Potturu Signed-off-by: Venkata Prasad Potturu Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Introduce sc8280xp TLMM driver

2022-03-15T01:03:46Z

The SC8280XP comes, like all other Qualcomm platforms, with a TLMM block, so add a driver for it. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220308221132.1423218-2-bjorn.andersson@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add SM8450 pinctrl driver

2021-12-09T02:01:30Z

This adds pincontrol driver for tlmm block found in SM8450 SoC This patch is based on initial code downstream by Elliot Berman Signed-off-by: Vinod Koul Tested-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211201072434.3968768-3-vkoul@kernel.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add SDX65 pincontrol driver

2021-11-21T22:48:27Z

Add initial Qualcomm SDX65 pinctrl driver to support pin configuration with pinctrl framework for SDX65 SoC. Signed-off-by: Vamsi Krishna Lanka Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/13acb3cb36349487dee9745ab040d8f1344d2096.1637048107.git.quic_vamslank@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: Add QCM2290 pinctrl driver

2021-09-23T21:13:24Z

It's a porting of pinctrl-scuba driver from CAF msm-4.19 kernel. The egpio and wake bits are removed. Signed-off-by: Shawn Guo Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923033224.29719-3-shawn.guo@linaro.org Signed-off-by: Linus Walleij