<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/pinctrl/qcom, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/pinctrl/qcom?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/pinctrl/qcom?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-05-19T12:52:10Z</updated>
<entry>
<title>pinctrl: qcom: spmi-gpio: Add pm6125 compatible</title>
<updated>2022-05-19T12:52:10Z</updated>
<author>
<name>Marijn Suijten</name>
<email>marijn.suijten@somainline.org</email>
</author>
<published>2022-05-11T22:06:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4d8a768ef4ed80112ffaa13a677196faa9d651c3'/>
<id>urn:sha1:4d8a768ef4ed80112ffaa13a677196faa9d651c3</id>
<content type='text'>
The pm6125 has 9 GPIOs with no holes inbetween.

Signed-off-by: Marijn Suijten &lt;marijn.suijten@somainline.org&gt;
Reviewed-by: AngeloGioacchino Del Regno &lt;angelogioacchino.delregno@somainline.org&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/20220511220613.1015472-4-marijn.suijten@somainline.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'irq/gpio-immutable' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into devel</title>
<updated>2022-05-05T14:50:14Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2022-05-05T14:50:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=160625856d324c27888ccbbe7693475b2706bd3b'/>
<id>urn:sha1:160625856d324c27888ccbbe7693475b2706bd3b</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Merge tag 'v5.18-rc5' into devel</title>
<updated>2022-05-01T21:25:10Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2022-05-01T21:25:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f930b69a8944ab3f018e2a175ddbd16e71348df9'/>
<id>urn:sha1:f930b69a8944ab3f018e2a175ddbd16e71348df9</id>
<content type='text'>
Merge in Linux 5.18-rc5 since new code to the STM32 driver
depend in a non-trivial way on the fixes merged in -rc5.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Update clock voting as optional</title>
<updated>2022-04-22T22:04:44Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=a6a5c1737fa914751aa9303ad9ee605244e05aa4'/>
<id>urn:sha1:a6a5c1737fa914751aa9303ad9ee605244e05aa4</id>
<content type='text'>
Update bulk clock voting to optional voting as ADSP bypass platform doesn't
need macro and decodec clocks, as these macro and dcodec GDSC switches are
maintained as power domains and operated from lpass clock drivers.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Reviewed-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-8-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Add SC7280 lpass pin configuration</title>
<updated>2022-04-22T22:04:43Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:06Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=120a5f2e5430ca3908d8b7639105d95f12ac135c'/>
<id>urn:sha1:120a5f2e5430ca3908d8b7639105d95f12ac135c</id>
<content type='text'>
Add pin control support for SC7280 LPASS LPI.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-7-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Extract chip specific LPASS LPI code</title>
<updated>2022-04-22T22:04:43Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9ce49018c6928263d41b783c9e4928c6af05db43'/>
<id>urn:sha1:9ce49018c6928263d41b783c9e4928c6af05db43</id>
<content type='text'>
Extract the chip specific SM8250 data from the LPASS LPI pinctrl driver
to allow reusing the common code in the addition of subsequent
platforms.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-6-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Update lpi pin group custiom functions with framework generic functions</title>
<updated>2022-04-22T22:04:43Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=be73368d535614b351c13a10680b4cdd06db2417'/>
<id>urn:sha1:be73368d535614b351c13a10680b4cdd06db2417</id>
<content type='text'>
Update custom pin group structure members with framework generic
group_desc structure and replace the driver's custom pinctrl_ops
with framework provided generic pin control group functions to avoid
redundant code written in lpass lpi driver.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Matthias Kaehlcke &lt;mka@chromium.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-5-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom: Update macro name to LPI specific</title>
<updated>2022-04-22T22:04:43Z</updated>
<author>
<name>Srinivasa Rao Mandadapu</name>
<email>quic_srivasam@quicinc.com</email>
</author>
<published>2022-04-18T12:37:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=6454711015267fe38b6f05aba232e01be2cb9693'/>
<id>urn:sha1:6454711015267fe38b6f05aba232e01be2cb9693</id>
<content type='text'>
Update NO_SLEW macro to LPI_NO_SLEW macro as this driver lpi specific.

Signed-off-by: Srinivasa Rao Mandadapu &lt;quic_srivasam@quicinc.com&gt;
Co-developed-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Signed-off-by: Venkata Prasad Potturu &lt;quic_potturu@quicinc.com&gt;
Reviewed-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Link: https://lore.kernel.org/r/1650285427-19752-4-git-send-email-quic_srivasam@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: qcom-pmic-gpio: Add support for pmx65</title>
<updated>2022-04-21T14:12:08Z</updated>
<author>
<name>Rohit Agarwal</name>
<email>quic_rohiagar@quicinc.com</email>
</author>
<published>2022-04-04T05:04:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=203638fd47f1cf20767674050cb78125676959b2'/>
<id>urn:sha1:203638fd47f1cf20767674050cb78125676959b2</id>
<content type='text'>
PMX65 pmic support gpio controller so add compatible.

Signed-off-by: Rohit Agarwal &lt;quic_rohiagar@quicinc.com&gt;
Link: https://lore.kernel.org/r/1649048650-14059-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: msmgpio: Make the irqchip immutable</title>
<updated>2022-04-19T14:22:26Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-04-19T14:18:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=14dbe186b9d42cbf662eae5a4da14687edbf0edb'/>
<id>urn:sha1:14dbe186b9d42cbf662eae5a4da14687edbf0edb</id>
<content type='text'>
Prevent gpiolib from messing with the irqchip by advertising
the irq_chip structure as immutable, making it const, and adding
the various calls that gpiolib relies upon.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20220419141846.598305-8-maz@kernel.org
</content>
</entry>
</feed>
