linux-dev/drivers/platform/x86/intel_pmc_core.h, branch linus/master

platform/x86: intel_pmc_core: Move to intel sub-directory

2021-08-20T18:00:21Z

Move Intel PMC core driver to intel sub-directory to improve readability. Signed-off-by: Kate Hsuan Reviewed-by: Hans de Goede Signed-off-by: Andy Shevchenko Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20210820110458.73018-7-andriy.shevchenko@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Prevent possibile overflow

2021-08-17T18:53:10Z

Substate priority levels are encoded in 4 bits in the LPM_PRI register. This value was used as an index to an array whose element size was less than 16, leading to the possibility of overflow should we read a larger than expected priority. In addition to the overflow, bad values could lead to incorrect state reporting. So rework the priority code to prevent the overflow and perform some validation of the register. Use the priority register values if they give an ordering of unique numbers between 0 and the maximum number of states. Otherwise, use a default ordering instead. Reported-by: Evgeny Novikov Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210814014728.520856-1-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake

2021-04-19T08:44:28Z

Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information and supports a few additional registers. Hence add the LTR registers specific to Tiger Lake to the cnp_ltr_show_map[]. Also adjust the number of LTR IPs for Tiger Lake to the correct amount. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Hans de Goede Acked-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20210417031252.3020837-9-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Add option to set/clear LPM mode

2021-04-19T08:44:28Z

By default the Low Power Mode (LPM or sub-state) status registers will latch condition status on every entry into Package C10. This is configurable in the PMC to allow latching on any achievable sub-state. Add a debugfs file to support this. Also add the option to clear the status registers to 0. Clearing the status registers before testing removes ambiguity around when the current values were set. The new file, latch_lpm_mode, looks like this: [c10] S0i2.0 S0i3.0 S0i2.1 S0i3.1 S0i3.2 clear Signed-off-by: David E. Box Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20210417031252.3020837-8-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Get LPM requirements for Tiger Lake

2021-04-19T08:44:28Z

Platforms that support low power modes (LPM) such as Tiger Lake maintain requirements for each sub-state that a readable in the PMC. However, unlike LPM status registers, requirement registers are not memory mapped but are available from an ACPI _DSM. Collect the requirements for Tiger Lake using the _DSM method and store in a buffer. Signed-off-by: Gayatri Kammela Co-developed-by: David E. Box Signed-off-by: David E. Box Reviewed-by: Hans de Goede Link: https://lore.kernel.org/r/20210417031252.3020837-6-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Show LPM residency in microseconds

2021-04-19T08:41:24Z

Modify the low power mode (LPM or sub-state) residency counters to display in microseconds just like the slp_s0_residency counter. The granularity of the counter is approximately 30.5us per tick. Double this value then divide by two to maintain accuracy. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Hans de Goede Reviewed-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20210417031252.3020837-5-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Handle sub-states generically

2021-04-19T08:41:24Z

The current implementation of pmc_core_substate_res_show() is written specifically for Tiger Lake. However, new platform will also have sub-states and may support different modes. Therefore rewrite the code to handle sub-states generically. Obtain the number and type of enabled states form the PMC. Use the Low Power Mode (LPM) priority register to store the states in order from shallowest to deepest for displays. Add a for_each macro to simplify this. While changing the sub-state display it makes sense to show only the "enabled" sub-states instead of showing all possible ones. After this patch, the debugfs file looks like this: Substate Residency S0i2.0 0 S0i3.0 0 S0i2.1 9329279 S0i3.1 0 S0i3.2 0 Suggested-by: David E. Box Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Hans de Goede Acked-by: Rajneesh Bhardwaj Link: https://lore.kernel.org/r/20210417031252.3020837-4-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file

2021-04-13T07:26:40Z

During PCH (platform/board) manufacturing process a global platform reset has to be induced in order for the configuration changes take the effect upon following platform reset. This is an internal platform state and is not intended to be used in the regular platform resets. The setting is exposed via ETR3 (Extended Test Mode Register 3). After the manufacturing process is completed the register cannot be written anymore and is hardware locked. This setting was commonly done by accessing PMC registers via /dev/mem but due to security concerns /dev/mem access is much more restricted, hence the reason for exposing this setting via the dedicated sysfs interface. To prevent post manufacturing abuse the register is protected by hardware locking and the file is set to read-only mode via is_visible handler. The register in MMIO space is defined for Cannon Lake and newer PCHs. Cc: Hans de Goede Cc: David E Box Reviewed-by: Andy Shevchenko Signed-off-by: Tamar Mashiah Signed-off-by: Tomas Winkler Link: https://lore.kernel.org/r/20210411141532.3004893-1-tomas.winkler@intel.com Reviewed-by: Hans de Goede Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: Fix the slp_s0 counter displayed value

2020-10-07T21:06:29Z

slp_s0 counter value displayed via debugfs interface is calculated by multiplying the granularity for crystal oscillator tick as 100us with the value read from using slp_s0 offset. But the granularity of the tick varies from platform to platform and it needs to be fixed. Hence, specify granularity of the tick for each platform, so that the value of the slp_s0 counter is accurate. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box Reviewed-by: Andy Shevchenko Link: https://lore.kernel.org/r/20201006224702.12697-4-david.e.box@linux.intel.com Signed-off-by: Hans de Goede

platform/x86: intel_pmc_core: avoid unused-function warnings

2020-05-05T12:33:24Z

When both CONFIG_DEBUG_FS and CONFIG_PM_SLEEP are disabled, the functions that got moved out of the #ifdef section now cause a warning: drivers/platform/x86/intel_pmc_core.c:654:13: error: 'pmc_core_lpm_display' defined but not used [-Werror=unused-function] 654 | static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev, | ^~~~~~~~~~~~~~~~~~~~ drivers/platform/x86/intel_pmc_core.c:617:13: error: 'pmc_core_slps0_display' defined but not used [-Werror=unused-function] 617 | static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev, | ^~~~~~~~~~~~~~~~~~~~~~ Rather than add even more #ifdefs here, remove them entirely and let the compiler work it out, it can actually get rid of all the debugfs calls without problems as long as the struct member is there. The two PM functions just need a __maybe_unused annotations to avoid another warning instead of the #ifdef. Fixes: aae43c2bcdc1 ("platform/x86: intel_pmc_core: Relocate pmc_core_*_display() to outside of CONFIG_DEBUG_FS") Signed-off-by: Arnd Bergmann Signed-off-by: Andy Shevchenko