<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/soc/sifive/Makefile, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/soc/sifive/Makefile?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/soc/sifive/Makefile?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2019-12-20T11:40:24Z</updated>
<entry>
<title>riscv: move sifive_l2_cache.c to drivers/soc</title>
<updated>2019-12-20T11:40:24Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2019-11-07T09:20:39Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9209fb51896fe0eef8dfac85afe1f357e9265c0d'/>
<id>urn:sha1:9209fb51896fe0eef8dfac85afe1f357e9265c0d</id>
<content type='text'>
The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management.  It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.

Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.

Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Borislav Petkov &lt;bp@suse.de&gt;
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
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